Bug Summary

File:build/gcc/rtlanal.c
Warning:line 5181, column 45
The result of the left shift is undefined because the right operand is negative

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-unknown-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name rtlanal.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -fno-split-dwarf-inlining -debugger-tuning=gdb -resource-dir /usr/lib64/clang/11.0.0 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/10/../../../../include/c++/10 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/10/../../../../include/c++/10/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/10/../../../../include/c++/10/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib64/clang/11.0.0/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-error=format-diag -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -o /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2021-01-16-135054-17580-1/report-2qEWHs.plist -x c++ /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c

/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c

1/* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2021 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
8Software Foundation; either version 3, or (at your option) any later
9version.
10
11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14for more details.
15
16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
19
20
21#include "config.h"
22#include "system.h"
23#include "coretypes.h"
24#include "backend.h"
25#include "target.h"
26#include "rtl.h"
27#include "rtlanal.h"
28#include "tree.h"
29#include "predict.h"
30#include "df.h"
31#include "memmodel.h"
32#include "tm_p.h"
33#include "insn-config.h"
34#include "regs.h"
35#include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
36#include "recog.h"
37#include "addresses.h"
38#include "rtl-iter.h"
39#include "hard-reg-set.h"
40#include "function-abi.h"
41
42/* Forward declarations */
43static void set_of_1 (rtx, const_rtx, void *);
44static bool covers_regno_p (const_rtx, unsigned int);
45static bool covers_regno_no_parallel_p (const_rtx, unsigned int);
46static int computed_jump_p_1 (const_rtx);
47static void parms_set (rtx, const_rtx, void *);
48
49static unsigned HOST_WIDE_INTlong cached_nonzero_bits (const_rtx, scalar_int_mode,
50 const_rtx, machine_mode,
51 unsigned HOST_WIDE_INTlong);
52static unsigned HOST_WIDE_INTlong nonzero_bits1 (const_rtx, scalar_int_mode,
53 const_rtx, machine_mode,
54 unsigned HOST_WIDE_INTlong);
55static unsigned int cached_num_sign_bit_copies (const_rtx, scalar_int_mode,
56 const_rtx, machine_mode,
57 unsigned int);
58static unsigned int num_sign_bit_copies1 (const_rtx, scalar_int_mode,
59 const_rtx, machine_mode,
60 unsigned int);
61
62rtx_subrtx_bound_info rtx_all_subrtx_bounds[NUM_RTX_CODE((int) LAST_AND_UNUSED_RTX_CODE)];
63rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds[NUM_RTX_CODE((int) LAST_AND_UNUSED_RTX_CODE)];
64
65/* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
66 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
67 SIGN_EXTEND then while narrowing we also have to enforce the
68 representation and sign-extend the value to mode DESTINATION_REP.
69
70 If the value is already sign-extended to DESTINATION_REP mode we
71 can just switch to DESTINATION mode on it. For each pair of
72 integral modes SOURCE and DESTINATION, when truncating from SOURCE
73 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
74 contains the number of high-order bits in SOURCE that have to be
75 copies of the sign-bit so that we can do this mode-switch to
76 DESTINATION. */
77
78static unsigned int
79num_sign_bit_copies_in_rep[MAX_MODE_INT + 1][MAX_MODE_INT + 1];
80
81/* Store X into index I of ARRAY. ARRAY is known to have at least I
82 elements. Return the new base of ARRAY. */
83
84template <typename T>
85typename T::value_type *
86generic_subrtx_iterator <T>::add_single_to_queue (array_type &array,
87 value_type *base,
88 size_t i, value_type x)
89{
90 if (base == array.stack)
91 {
92 if (i < LOCAL_ELEMS)
93 {
94 base[i] = x;
95 return base;
96 }
97 gcc_checking_assert (i == LOCAL_ELEMS)((void)(!(i == LOCAL_ELEMS) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 97, __FUNCTION__), 0 : 0))
;
98 /* A previous iteration might also have moved from the stack to the
99 heap, in which case the heap array will already be big enough. */
100 if (vec_safe_length (array.heap) <= i)
101 vec_safe_grow (array.heap, i + 1, true);
102 base = array.heap->address ();
103 memcpy (base, array.stack, sizeof (array.stack));
104 base[LOCAL_ELEMS] = x;
105 return base;
106 }
107 unsigned int length = array.heap->length ();
108 if (length > i)
109 {
110 gcc_checking_assert (base == array.heap->address ())((void)(!(base == array.heap->address ()) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 110, __FUNCTION__), 0 : 0))
;
111 base[i] = x;
112 return base;
113 }
114 else
115 {
116 gcc_checking_assert (i == length)((void)(!(i == length) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 116, __FUNCTION__), 0 : 0))
;
117 vec_safe_push (array.heap, x);
118 return array.heap->address ();
119 }
120}
121
122/* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
123 number of elements added to the worklist. */
124
125template <typename T>
126size_t
127generic_subrtx_iterator <T>::add_subrtxes_to_queue (array_type &array,
128 value_type *base,
129 size_t end, rtx_type x)
130{
131 enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
132 const char *format = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
133 size_t orig_end = end;
134 if (__builtin_expect (INSN_P (x)(((((enum rtx_code) (x)->code) == INSN) || (((enum rtx_code
) (x)->code) == JUMP_INSN) || (((enum rtx_code) (x)->code
) == CALL_INSN)) || (((enum rtx_code) (x)->code) == DEBUG_INSN
))
, false))
135 {
136 /* Put the pattern at the top of the queue, since that's what
137 we're likely to want most. It also allows for the SEQUENCE
138 code below. */
139 for (int i = GET_RTX_LENGTH (GET_CODE (x))(rtx_length[(int) (((enum rtx_code) (x)->code))]) - 1; i >= 0; --i)
140 if (format[i] == 'e')
141 {
142 value_type subx = T::get_value (x->u.fld[i].rt_rtx);
143 if (__builtin_expect (end < LOCAL_ELEMS, true))
144 base[end++] = subx;
145 else
146 base = add_single_to_queue (array, base, end++, subx);
147 }
148 }
149 else
150 for (int i = 0; format[i]; ++i)
151 if (format[i] == 'e')
152 {
153 value_type subx = T::get_value (x->u.fld[i].rt_rtx);
154 if (__builtin_expect (end < LOCAL_ELEMS, true))
155 base[end++] = subx;
156 else
157 base = add_single_to_queue (array, base, end++, subx);
158 }
159 else if (format[i] == 'E')
160 {
161 unsigned int length = GET_NUM_ELEM (x->u.fld[i].rt_rtvec)((x->u.fld[i].rt_rtvec)->num_elem);
162 rtx *vec = x->u.fld[i].rt_rtvec->elem;
163 if (__builtin_expect (end + length <= LOCAL_ELEMS, true))
164 for (unsigned int j = 0; j < length; j++)
165 base[end++] = T::get_value (vec[j]);
166 else
167 for (unsigned int j = 0; j < length; j++)
168 base = add_single_to_queue (array, base, end++,
169 T::get_value (vec[j]));
170 if (code == SEQUENCE && end == length)
171 /* If the subrtxes of the sequence fill the entire array then
172 we know that no other parts of a containing insn are queued.
173 The caller is therefore iterating over the sequence as a
174 PATTERN (...), so we also want the patterns of the
175 subinstructions. */
176 for (unsigned int j = 0; j < length; j++)
177 {
178 typename T::rtx_type x = T::get_rtx (base[j]);
179 if (INSN_P (x)(((((enum rtx_code) (x)->code) == INSN) || (((enum rtx_code
) (x)->code) == JUMP_INSN) || (((enum rtx_code) (x)->code
) == CALL_INSN)) || (((enum rtx_code) (x)->code) == DEBUG_INSN
))
)
180 base[j] = T::get_value (PATTERN (x));
181 }
182 }
183 return end - orig_end;
184}
185
186template <typename T>
187void
188generic_subrtx_iterator <T>::free_array (array_type &array)
189{
190 vec_free (array.heap);
191}
192
193template <typename T>
194const size_t generic_subrtx_iterator <T>::LOCAL_ELEMS;
195
196template class generic_subrtx_iterator <const_rtx_accessor>;
197template class generic_subrtx_iterator <rtx_var_accessor>;
198template class generic_subrtx_iterator <rtx_ptr_accessor>;
199
200/* Return 1 if the value of X is unstable
201 (would be different at a different point in the program).
202 The frame pointer, arg pointer, etc. are considered stable
203 (within one function) and so is anything marked `unchanging'. */
204
205int
206rtx_unstable_p (const_rtx x)
207{
208 const RTX_CODEenum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
209 int i;
210 const char *fmt;
211
212 switch (code)
213 {
214 case MEM:
215 return !MEM_READONLY_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 215, __FUNCTION__); _rtx; })->unchanging)
|| rtx_unstable_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));
216
217 case CONST:
218 CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR
:
219 case SYMBOL_REF:
220 case LABEL_REF:
221 return 0;
222
223 case REG:
224 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
225 if (x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER]) || x == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER])
226 /* The arg pointer varies if it is not a fixed register. */
227 || (x == arg_pointer_rtx((this_target_rtl->x_global_rtl)[GR_ARG_POINTER]) && fixed_regs(this_target_hard_regs->x_fixed_regs)[ARG_POINTER_REGNUM16]))
228 return 0;
229 /* ??? When call-clobbered, the value is stable modulo the restore
230 that must happen after a call. This currently screws up local-alloc
231 into believing that the restore is not needed. */
232 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED0 && x == pic_offset_table_rtx(this_target_rtl->x_pic_offset_table_rtx))
233 return 0;
234 return 1;
235
236 case ASM_OPERANDS:
237 if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 237, __FUNCTION__); _rtx; })->volatil)
)
238 return 1;
239
240 /* Fall through. */
241
242 default:
243 break;
244 }
245
246 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
247 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
248 if (fmt[i] == 'e')
249 {
250 if (rtx_unstable_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx)))
251 return 1;
252 }
253 else if (fmt[i] == 'E')
254 {
255 int j;
256 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
257 if (rtx_unstable_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])))
258 return 1;
259 }
260
261 return 0;
262}
263
264/* Return 1 if X has a value that can vary even between two
265 executions of the program. 0 means X can be compared reliably
266 against certain constants or near-constants.
267 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
268 zero, we are slightly more conservative.
269 The frame pointer and the arg pointer are considered constant. */
270
271bool
272rtx_varies_p (const_rtx x, bool for_alias)
273{
274 RTX_CODEenum rtx_code code;
275 int i;
276 const char *fmt;
277
278 if (!x)
279 return 0;
280
281 code = GET_CODE (x)((enum rtx_code) (x)->code);
282 switch (code)
283 {
284 case MEM:
285 return !MEM_READONLY_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 285, __FUNCTION__); _rtx; })->unchanging)
|| rtx_varies_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), for_alias);
286
287 case CONST:
288 CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR
:
289 case SYMBOL_REF:
290 case LABEL_REF:
291 return 0;
292
293 case REG:
294 /* Note that we have to test for the actual rtx used for the frame
295 and arg pointers and not just the register number in case we have
296 eliminated the frame and/or arg pointer and are using it
297 for pseudos. */
298 if (x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER]) || x == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER])
299 /* The arg pointer varies if it is not a fixed register. */
300 || (x == arg_pointer_rtx((this_target_rtl->x_global_rtl)[GR_ARG_POINTER]) && fixed_regs(this_target_hard_regs->x_fixed_regs)[ARG_POINTER_REGNUM16]))
301 return 0;
302 if (x == pic_offset_table_rtx(this_target_rtl->x_pic_offset_table_rtx)
303 /* ??? When call-clobbered, the value is stable modulo the restore
304 that must happen after a call. This currently screws up
305 local-alloc into believing that the restore is not needed, so we
306 must return 0 only if we are called from alias analysis. */
307 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED0 || for_alias))
308 return 0;
309 return 1;
310
311 case LO_SUM:
312 /* The operand 0 of a LO_SUM is considered constant
313 (in fact it is related specifically to operand 1)
314 during alias analysis. */
315 return (! for_alias && rtx_varies_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), for_alias))
316 || rtx_varies_p (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), for_alias);
317
318 case ASM_OPERANDS:
319 if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 319, __FUNCTION__); _rtx; })->volatil)
)
320 return 1;
321
322 /* Fall through. */
323
324 default:
325 break;
326 }
327
328 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
329 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
330 if (fmt[i] == 'e')
331 {
332 if (rtx_varies_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), for_alias))
333 return 1;
334 }
335 else if (fmt[i] == 'E')
336 {
337 int j;
338 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
339 if (rtx_varies_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), for_alias))
340 return 1;
341 }
342
343 return 0;
344}
345
346/* Compute an approximation for the offset between the register
347 FROM and TO for the current function, as it was at the start
348 of the routine. */
349
350static poly_int64
351get_initial_register_offset (int from, int to)
352{
353 static const struct elim_table_t
354 {
355 const int from;
356 const int to;
357 } table[] = ELIMINABLE_REGS{{ 16, 7}, { 16, 6}, { 19, 7}, { 19, 6}};
358 poly_int64 offset1, offset2;
359 unsigned int i, j;
360
361 if (to == from)
362 return 0;
363
364 /* It is not safe to call INITIAL_ELIMINATION_OFFSET before the epilogue
365 is completed, but we need to give at least an estimate for the stack
366 pointer based on the frame size. */
367 if (!epilogue_completed)
368 {
369 offset1 = crtl(&x_rtl)->outgoing_args_size + get_frame_size ();
370#if !STACK_GROWS_DOWNWARD1
371 offset1 = - offset1;
372#endif
373 if (to == STACK_POINTER_REGNUM7)
374 return offset1;
375 else if (from == STACK_POINTER_REGNUM7)
376 return - offset1;
377 else
378 return 0;
379 }
380
381 for (i = 0; i < ARRAY_SIZE (table)(sizeof (table) / sizeof ((table)[0])); i++)
382 if (table[i].from == from)
383 {
384 if (table[i].to == to)
385 {
386 INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
387 offset1)((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
;
388 return offset1;
389 }
390 for (j = 0; j < ARRAY_SIZE (table)(sizeof (table) / sizeof ((table)[0])); j++)
391 {
392 if (table[j].to == to
393 && table[j].from == table[i].to)
394 {
395 INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
396 offset1)((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
;
397 INITIAL_ELIMINATION_OFFSET (table[j].from, table[j].to,((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)))
398 offset2)((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)))
;
399 return offset1 + offset2;
400 }
401 if (table[j].from == to
402 && table[j].to == table[i].to)
403 {
404 INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
405 offset1)((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
;
406 INITIAL_ELIMINATION_OFFSET (table[j].from, table[j].to,((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)))
407 offset2)((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)))
;
408 return offset1 - offset2;
409 }
410 }
411 }
412 else if (table[i].to == from)
413 {
414 if (table[i].from == to)
415 {
416 INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
417 offset1)((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
;
418 return - offset1;
419 }
420 for (j = 0; j < ARRAY_SIZE (table)(sizeof (table) / sizeof ((table)[0])); j++)
421 {
422 if (table[j].to == to
423 && table[j].from == table[i].from)
424 {
425 INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
426 offset1)((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
;
427 INITIAL_ELIMINATION_OFFSET (table[j].from, table[j].to,((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)))
428 offset2)((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)))
;
429 return - offset1 + offset2;
430 }
431 if (table[j].from == to
432 && table[j].to == table[i].from)
433 {
434 INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
435 offset1)((offset1) = ix86_initial_elimination_offset ((table[i].from)
, (table[i].to)))
;
436 INITIAL_ELIMINATION_OFFSET (table[j].from, table[j].to,((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)))
437 offset2)((offset2) = ix86_initial_elimination_offset ((table[j].from)
, (table[j].to)))
;
438 return - offset1 - offset2;
439 }
440 }
441 }
442
443 /* If the requested register combination was not found,
444 try a different more simple combination. */
445 if (from == ARG_POINTER_REGNUM16)
446 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM6, to);
447 else if (to == ARG_POINTER_REGNUM16)
448 return get_initial_register_offset (from, HARD_FRAME_POINTER_REGNUM6);
449 else if (from == HARD_FRAME_POINTER_REGNUM6)
450 return get_initial_register_offset (FRAME_POINTER_REGNUM19, to);
451 else if (to == HARD_FRAME_POINTER_REGNUM6)
452 return get_initial_register_offset (from, FRAME_POINTER_REGNUM19);
453 else
454 return 0;
455}
456
457/* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE
458 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
459 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory
460 references on strict alignment machines. */
461
462static int
463rtx_addr_can_trap_p_1 (const_rtx x, poly_int64 offset, poly_int64 size,
464 machine_mode mode, bool unaligned_mems)
465{
466 enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
467 gcc_checking_assert (mode == BLKmode || known_size_p (size))((void)(!(mode == ((void) 0, E_BLKmode) || known_size_p (size
)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 467, __FUNCTION__), 0 : 0))
;
468 poly_int64 const_x1;
469
470 /* The offset must be a multiple of the mode size if we are considering
471 unaligned memory references on strict alignment machines. */
472 if (STRICT_ALIGNMENT0 && unaligned_mems && mode != BLKmode((void) 0, E_BLKmode))
473 {
474 poly_int64 actual_offset = offset;
475
476#ifdef SPARC_STACK_BOUNDARY_HACK
477 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
478 the real alignment of %sp. However, when it does this, the
479 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
480 if (SPARC_STACK_BOUNDARY_HACK
481 && (x == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]) || x == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER])))
482 actual_offset -= STACK_POINTER_OFFSET0;
483#endif
484
485 if (!multiple_p (actual_offset, GET_MODE_SIZE (mode)))
486 return 1;
487 }
488
489 switch (code)
490 {
491 case SYMBOL_REF:
492 if (SYMBOL_REF_WEAK (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
("SYMBOL_REF_WEAK", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 492, __FUNCTION__); _rtx; })->return_val)
)
493 return 1;
494 if (!CONSTANT_POOL_ADDRESS_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
("CONSTANT_POOL_ADDRESS_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 494, __FUNCTION__); _rtx; })->unchanging)
&& !SYMBOL_REF_FUNCTION_P (x)(((__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((
enum rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
("SYMBOL_REF_FLAGS", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 494, __FUNCTION__); _rtx; }) ->u2.symbol_ref_flags) &
(1 << 0)) != 0)
)
495 {
496 tree decl;
497 poly_int64 decl_size;
498
499 if (maybe_lt (offset, 0))
500 return 1;
501 if (!known_size_p (size))
502 return maybe_ne (offset, 0);
503
504 /* If the size of the access or of the symbol is unknown,
505 assume the worst. */
506 decl = SYMBOL_REF_DECL (x)((__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
("CONSTANT_POOL_ADDRESS_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 506, __FUNCTION__); _rtx; })->unchanging) ? nullptr : ((
((x))->u.fld[1]).rt_tree))
;
507
508 /* Else check that the access is in bounds. TODO: restructure
509 expr_size/tree_expr_size/int_expr_size and just use the latter. */
510 if (!decl)
511 decl_size = -1;
512 else if (DECL_P (decl)(tree_code_type[(int) (((enum tree_code) (decl)->base.code
))] == tcc_declaration)
&& DECL_SIZE_UNIT (decl)((contains_struct_check ((decl), (TS_DECL_COMMON), "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 512, __FUNCTION__))->decl_common.size_unit)
)
513 {
514 if (!poly_int_tree_p (DECL_SIZE_UNIT (decl)((contains_struct_check ((decl), (TS_DECL_COMMON), "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 514, __FUNCTION__))->decl_common.size_unit)
, &decl_size))
515 decl_size = -1;
516 }
517 else if (TREE_CODE (decl)((enum tree_code) (decl)->base.code) == STRING_CST)
518 decl_size = TREE_STRING_LENGTH (decl)((tree_check ((decl), "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 518, __FUNCTION__, (STRING_CST)))->string.length)
;
519 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl))((tree_class_check ((((contains_struct_check ((decl), (TS_TYPED
), "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 519, __FUNCTION__))->typed.type)), (tcc_type), "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 519, __FUNCTION__))->type_common.size_unit)
)
520 decl_size = int_size_in_bytes (TREE_TYPE (decl)((contains_struct_check ((decl), (TS_TYPED), "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 520, __FUNCTION__))->typed.type)
);
521 else
522 decl_size = -1;
523
524 return (!known_size_p (decl_size) || known_eq (decl_size, 0)(!maybe_ne (decl_size, 0))
525 ? maybe_ne (offset, 0)
526 : !known_subrange_p (offset, size, 0, decl_size));
527 }
528
529 return 0;
530
531 case LABEL_REF:
532 return 0;
533
534 case REG:
535 /* Stack references are assumed not to trap, but we need to deal with
536 nonsensical offsets. */
537 if (x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER]) || x == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER])
538 || x == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])
539 /* The arg pointer varies if it is not a fixed register. */
540 || (x == arg_pointer_rtx((this_target_rtl->x_global_rtl)[GR_ARG_POINTER]) && fixed_regs(this_target_hard_regs->x_fixed_regs)[ARG_POINTER_REGNUM16]))
541 {
542#ifdef RED_ZONE_SIZE128
543 poly_int64 red_zone_size = RED_ZONE_SIZE128;
544#else
545 poly_int64 red_zone_size = 0;
546#endif
547 poly_int64 stack_boundary = PREFERRED_STACK_BOUNDARYix86_preferred_stack_boundary / BITS_PER_UNIT(8);
548 poly_int64 low_bound, high_bound;
549
550 if (!known_size_p (size))
551 return 1;
552
553 if (x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER]))
554 {
555 if (FRAME_GROWS_DOWNWARD1)
556 {
557 high_bound = targetm.starting_frame_offset ();
558 low_bound = high_bound - get_frame_size ();
559 }
560 else
561 {
562 low_bound = targetm.starting_frame_offset ();
563 high_bound = low_bound + get_frame_size ();
564 }
565 }
566 else if (x == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER]))
567 {
568 poly_int64 sp_offset
569 = get_initial_register_offset (STACK_POINTER_REGNUM7,
570 HARD_FRAME_POINTER_REGNUM6);
571 poly_int64 ap_offset
572 = get_initial_register_offset (ARG_POINTER_REGNUM16,
573 HARD_FRAME_POINTER_REGNUM6);
574
575#if STACK_GROWS_DOWNWARD1
576 low_bound = sp_offset - red_zone_size - stack_boundary;
577 high_bound = ap_offset
578 + FIRST_PARM_OFFSET (current_function_decl)0
579#if !ARGS_GROW_DOWNWARD0
580 + crtl(&x_rtl)->args.size
581#endif
582 + stack_boundary;
583#else
584 high_bound = sp_offset + red_zone_size + stack_boundary;
585 low_bound = ap_offset
586 + FIRST_PARM_OFFSET (current_function_decl)0
587#if ARGS_GROW_DOWNWARD0
588 - crtl(&x_rtl)->args.size
589#endif
590 - stack_boundary;
591#endif
592 }
593 else if (x == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
594 {
595 poly_int64 ap_offset
596 = get_initial_register_offset (ARG_POINTER_REGNUM16,
597 STACK_POINTER_REGNUM7);
598
599#if STACK_GROWS_DOWNWARD1
600 low_bound = - red_zone_size - stack_boundary;
601 high_bound = ap_offset
602 + FIRST_PARM_OFFSET (current_function_decl)0
603#if !ARGS_GROW_DOWNWARD0
604 + crtl(&x_rtl)->args.size
605#endif
606 + stack_boundary;
607#else
608 high_bound = red_zone_size + stack_boundary;
609 low_bound = ap_offset
610 + FIRST_PARM_OFFSET (current_function_decl)0
611#if ARGS_GROW_DOWNWARD0
612 - crtl(&x_rtl)->args.size
613#endif
614 - stack_boundary;
615#endif
616 }
617 else
618 {
619 /* We assume that accesses are safe to at least the
620 next stack boundary.
621 Examples are varargs and __builtin_return_address. */
622#if ARGS_GROW_DOWNWARD0
623 high_bound = FIRST_PARM_OFFSET (current_function_decl)0
624 + stack_boundary;
625 low_bound = FIRST_PARM_OFFSET (current_function_decl)0
626 - crtl(&x_rtl)->args.size - stack_boundary;
627#else
628 low_bound = FIRST_PARM_OFFSET (current_function_decl)0
629 - stack_boundary;
630 high_bound = FIRST_PARM_OFFSET (current_function_decl)0
631 + crtl(&x_rtl)->args.size + stack_boundary;
632#endif
633 }
634
635 if (known_ge (offset, low_bound)(!maybe_lt (offset, low_bound))
636 && known_le (offset, high_bound - size)(!maybe_lt (high_bound - size, offset)))
637 return 0;
638 return 1;
639 }
640 /* All of the virtual frame registers are stack references. */
641 if (REGNO (x)(rhs_regno(x)) >= FIRST_VIRTUAL_REGISTER(76)
642 && REGNO (x)(rhs_regno(x)) <= LAST_VIRTUAL_REGISTER(((76)) + 5))
643 return 0;
644 return 1;
645
646 case CONST:
647 return rtx_addr_can_trap_p_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), offset, size,
648 mode, unaligned_mems);
649
650 case PLUS:
651 /* An address is assumed not to trap if:
652 - it is the pic register plus a const unspec without offset. */
653 if (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) == pic_offset_table_rtx(this_target_rtl->x_pic_offset_table_rtx)
654 && GET_CODE (XEXP (x, 1))((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST
655 && GET_CODE (XEXP (XEXP (x, 1), 0))((enum rtx_code) (((((((x)->u.fld[1]).rt_rtx))->u.fld[0
]).rt_rtx))->code)
== UNSPEC
656 && known_eq (offset, 0)(!maybe_ne (offset, 0)))
657 return 0;
658
659 /* - or it is an address that can't trap plus a constant integer. */
660 if (poly_int_rtx_p (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), &const_x1)
661 && !rtx_addr_can_trap_p_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), offset + const_x1,
662 size, mode, unaligned_mems))
663 return 0;
664
665 return 1;
666
667 case LO_SUM:
668 case PRE_MODIFY:
669 return rtx_addr_can_trap_p_1 (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), offset, size,
670 mode, unaligned_mems);
671
672 case PRE_DEC:
673 case PRE_INC:
674 case POST_DEC:
675 case POST_INC:
676 case POST_MODIFY:
677 return rtx_addr_can_trap_p_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), offset, size,
678 mode, unaligned_mems);
679
680 default:
681 break;
682 }
683
684 /* If it isn't one of the case above, it can cause a trap. */
685 return 1;
686}
687
688/* Return nonzero if the use of X as an address in a MEM can cause a trap. */
689
690int
691rtx_addr_can_trap_p (const_rtx x)
692{
693 return rtx_addr_can_trap_p_1 (x, 0, -1, BLKmode((void) 0, E_BLKmode), false);
694}
695
696/* Return true if X contains a MEM subrtx. */
697
698bool
699contains_mem_rtx_p (rtx x)
700{
701 subrtx_iterator::array_type array;
702 FOR_EACH_SUBRTX (iter, array, x, ALL)for (subrtx_iterator iter (array, x, rtx_all_subrtx_bounds); !
iter.at_end (); iter.next ())
703 if (MEM_P (*iter)(((enum rtx_code) (*iter)->code) == MEM))
704 return true;
705
706 return false;
707}
708
709/* Return true if X is an address that is known to not be zero. */
710
711bool
712nonzero_address_p (const_rtx x)
713{
714 const enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
715
716 switch (code)
717 {
718 case SYMBOL_REF:
719 return flag_delete_null_pointer_checksglobal_options.x_flag_delete_null_pointer_checks && !SYMBOL_REF_WEAK (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
("SYMBOL_REF_WEAK", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 719, __FUNCTION__); _rtx; })->return_val)
;
720
721 case LABEL_REF:
722 return true;
723
724 case REG:
725 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
726 if (x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER]) || x == hard_frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_HARD_FRAME_POINTER])
727 || x == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])
728 || (x == arg_pointer_rtx((this_target_rtl->x_global_rtl)[GR_ARG_POINTER]) && fixed_regs(this_target_hard_regs->x_fixed_regs)[ARG_POINTER_REGNUM16]))
729 return true;
730 /* All of the virtual frame registers are stack references. */
731 if (REGNO (x)(rhs_regno(x)) >= FIRST_VIRTUAL_REGISTER(76)
732 && REGNO (x)(rhs_regno(x)) <= LAST_VIRTUAL_REGISTER(((76)) + 5))
733 return true;
734 return false;
735
736 case CONST:
737 return nonzero_address_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));
738
739 case PLUS:
740 /* Handle PIC references. */
741 if (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) == pic_offset_table_rtx(this_target_rtl->x_pic_offset_table_rtx)
742 && CONSTANT_P (XEXP (x, 1))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
)
743 return true;
744 return false;
745
746 case PRE_MODIFY:
747 /* Similar to the above; allow positive offsets. Further, since
748 auto-inc is only allowed in memories, the register must be a
749 pointer. */
750 if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
751 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) > 0)
752 return true;
753 return nonzero_address_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));
754
755 case PRE_INC:
756 /* Similarly. Further, the offset is always positive. */
757 return true;
758
759 case PRE_DEC:
760 case POST_DEC:
761 case POST_INC:
762 case POST_MODIFY:
763 return nonzero_address_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));
764
765 case LO_SUM:
766 return nonzero_address_p (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx));
767
768 default:
769 break;
770 }
771
772 /* If it isn't one of the case above, might be zero. */
773 return false;
774}
775
776/* Return 1 if X refers to a memory location whose address
777 cannot be compared reliably with constant addresses,
778 or if X refers to a BLKmode memory object.
779 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
780 zero, we are slightly more conservative. */
781
782bool
783rtx_addr_varies_p (const_rtx x, bool for_alias)
784{
785 enum rtx_code code;
786 int i;
787 const char *fmt;
788
789 if (x == 0)
790 return 0;
791
792 code = GET_CODE (x)((enum rtx_code) (x)->code);
793 if (code == MEM)
794 return GET_MODE (x)((machine_mode) (x)->mode) == BLKmode((void) 0, E_BLKmode) || rtx_varies_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), for_alias);
795
796 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
797 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
798 if (fmt[i] == 'e')
799 {
800 if (rtx_addr_varies_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), for_alias))
801 return 1;
802 }
803 else if (fmt[i] == 'E')
804 {
805 int j;
806 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
807 if (rtx_addr_varies_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), for_alias))
808 return 1;
809 }
810 return 0;
811}
812
813/* Return the CALL in X if there is one. */
814
815rtx
816get_call_rtx_from (const rtx_insn *insn)
817{
818 rtx x = PATTERN (insn);
819 if (GET_CODE (x)((enum rtx_code) (x)->code) == PARALLEL)
820 x = XVECEXP (x, 0, 0)(((((x)->u.fld[0]).rt_rtvec))->elem[0]);
821 if (GET_CODE (x)((enum rtx_code) (x)->code) == SET)
822 x = SET_SRC (x)(((x)->u.fld[1]).rt_rtx);
823 if (GET_CODE (x)((enum rtx_code) (x)->code) == CALL && MEM_P (XEXP (x, 0))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == MEM
)
)
824 return x;
825 return NULL_RTX(rtx) 0;
826}
827
828/* Get the declaration of the function called by INSN. */
829
830tree
831get_call_fndecl (const rtx_insn *insn)
832{
833 rtx note, datum;
834
835 note = find_reg_note (insn, REG_CALL_DECL, NULL_RTX(rtx) 0);
836 if (note == NULL_RTX(rtx) 0)
837 return NULL_TREE(tree) nullptr;
838
839 datum = XEXP (note, 0)(((note)->u.fld[0]).rt_rtx);
840 if (datum != NULL_RTX(rtx) 0)
841 return SYMBOL_REF_DECL (datum)((__extension__ ({ __typeof ((datum)) const _rtx = ((datum));
if (((enum rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
("CONSTANT_POOL_ADDRESS_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 841, __FUNCTION__); _rtx; })->unchanging) ? nullptr : ((
((datum))->u.fld[1]).rt_tree))
;
842
843 return NULL_TREE(tree) nullptr;
844}
845
846/* Return the value of the integer term in X, if one is apparent;
847 otherwise return 0.
848 Only obvious integer terms are detected.
849 This is used in cse.c with the `related_value' field. */
850
851HOST_WIDE_INTlong
852get_integer_term (const_rtx x)
853{
854 if (GET_CODE (x)((enum rtx_code) (x)->code) == CONST)
855 x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
856
857 if (GET_CODE (x)((enum rtx_code) (x)->code) == MINUS
858 && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
)
859 return - INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]);
860 if (GET_CODE (x)((enum rtx_code) (x)->code) == PLUS
861 && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
)
862 return INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]);
863 return 0;
864}
865
866/* If X is a constant, return the value sans apparent integer term;
867 otherwise return 0.
868 Only obvious integer terms are detected. */
869
870rtx
871get_related_value (const_rtx x)
872{
873 if (GET_CODE (x)((enum rtx_code) (x)->code) != CONST)
874 return 0;
875 x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
876 if (GET_CODE (x)((enum rtx_code) (x)->code) == PLUS
877 && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
)
878 return XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
879 else if (GET_CODE (x)((enum rtx_code) (x)->code) == MINUS
880 && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
)
881 return XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
882 return 0;
883}
884
885/* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
886 to somewhere in the same object or object_block as SYMBOL. */
887
888bool
889offset_within_block_p (const_rtx symbol, HOST_WIDE_INTlong offset)
890{
891 tree decl;
892
893 if (GET_CODE (symbol)((enum rtx_code) (symbol)->code) != SYMBOL_REF)
894 return false;
895
896 if (offset == 0)
897 return true;
898
899 if (offset > 0)
900 {
901 if (CONSTANT_POOL_ADDRESS_P (symbol)(__extension__ ({ __typeof ((symbol)) const _rtx = ((symbol))
; if (((enum rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
("CONSTANT_POOL_ADDRESS_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 901, __FUNCTION__); _rtx; })->unchanging)
902 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
903 return true;
904
905 decl = SYMBOL_REF_DECL (symbol)((__extension__ ({ __typeof ((symbol)) const _rtx = ((symbol)
); if (((enum rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
("CONSTANT_POOL_ADDRESS_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 905, __FUNCTION__); _rtx; })->unchanging) ? nullptr : ((
((symbol))->u.fld[1]).rt_tree))
;
906 if (decl && offset < int_size_in_bytes (TREE_TYPE (decl)((contains_struct_check ((decl), (TS_TYPED), "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 906, __FUNCTION__))->typed.type)
))
907 return true;
908 }
909
910 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol)(((__extension__ ({ __typeof ((symbol)) const _rtx = ((symbol
)); if (((enum rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
("SYMBOL_REF_FLAGS", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 910, __FUNCTION__); _rtx; }) ->u2.symbol_ref_flags) &
(1 << 7)) != 0)
911 && SYMBOL_REF_BLOCK (symbol)((&(symbol)->u.block_sym)->block)
912 && SYMBOL_REF_BLOCK_OFFSET (symbol)((&(symbol)->u.block_sym)->offset) >= 0
913 && ((unsigned HOST_WIDE_INTlong) offset + SYMBOL_REF_BLOCK_OFFSET (symbol)((&(symbol)->u.block_sym)->offset)
914 < (unsigned HOST_WIDE_INTlong) SYMBOL_REF_BLOCK (symbol)((&(symbol)->u.block_sym)->block)->size))
915 return true;
916
917 return false;
918}
919
920/* Split X into a base and a constant offset, storing them in *BASE_OUT
921 and *OFFSET_OUT respectively. */
922
923void
924split_const (rtx x, rtx *base_out, rtx *offset_out)
925{
926 if (GET_CODE (x)((enum rtx_code) (x)->code) == CONST)
927 {
928 x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
929 if (GET_CODE (x)((enum rtx_code) (x)->code) == PLUS && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
)
930 {
931 *base_out = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
932 *offset_out = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);
933 return;
934 }
935 }
936 *base_out = x;
937 *offset_out = const0_rtx(const_int_rtx[64]);
938}
939
940/* Express integer value X as some value Y plus a polynomial offset,
941 where Y is either const0_rtx, X or something within X (as opposed
942 to a new rtx). Return the Y and store the offset in *OFFSET_OUT. */
943
944rtx
945strip_offset (rtx x, poly_int64_pod *offset_out)
946{
947 rtx base = const0_rtx(const_int_rtx[64]);
948 rtx test = x;
949 if (GET_CODE (test)((enum rtx_code) (test)->code) == CONST)
950 test = XEXP (test, 0)(((test)->u.fld[0]).rt_rtx);
951 if (GET_CODE (test)((enum rtx_code) (test)->code) == PLUS)
952 {
953 base = XEXP (test, 0)(((test)->u.fld[0]).rt_rtx);
954 test = XEXP (test, 1)(((test)->u.fld[1]).rt_rtx);
955 }
956 if (poly_int_rtx_p (test, offset_out))
957 return base;
958 *offset_out = 0;
959 return x;
960}
961
962/* Return the argument size in REG_ARGS_SIZE note X. */
963
964poly_int64
965get_args_size (const_rtx x)
966{
967 gcc_checking_assert (REG_NOTE_KIND (x) == REG_ARGS_SIZE)((void)(!(((enum reg_note) ((machine_mode) (x)->mode)) == REG_ARGS_SIZE
) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 967, __FUNCTION__), 0 : 0))
;
968 return rtx_to_poly_int64 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));
969}
970
971/* Return the number of places FIND appears within X. If COUNT_DEST is
972 zero, we do not count occurrences inside the destination of a SET. */
973
974int
975count_occurrences (const_rtx x, const_rtx find, int count_dest)
976{
977 int i, j;
978 enum rtx_code code;
979 const char *format_ptr;
980 int count;
981
982 if (x == find)
983 return 1;
984
985 code = GET_CODE (x)((enum rtx_code) (x)->code);
986
987 switch (code)
988 {
989 case REG:
990 CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR
:
991 case SYMBOL_REF:
992 case CODE_LABEL:
993 case PC:
994 case CC0:
995 return 0;
996
997 case EXPR_LIST:
998 count = count_occurrences (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), find, count_dest);
999 if (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx))
1000 count += count_occurrences (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), find, count_dest);
1001 return count;
1002
1003 case MEM:
1004 if (MEM_P (find)(((enum rtx_code) (find)->code) == MEM) && rtx_equal_p (x, find))
1005 return 1;
1006 break;
1007
1008 case SET:
1009 if (SET_DEST (x)(((x)->u.fld[0]).rt_rtx) == find && ! count_dest)
1010 return count_occurrences (SET_SRC (x)(((x)->u.fld[1]).rt_rtx), find, count_dest);
1011 break;
1012
1013 default:
1014 break;
1015 }
1016
1017 format_ptr = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
1018 count = 0;
1019
1020 for (i = 0; i < GET_RTX_LENGTH (code)(rtx_length[(int) (code)]); i++)
1021 {
1022 switch (*format_ptr++)
1023 {
1024 case 'e':
1025 count += count_occurrences (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), find, count_dest);
1026 break;
1027
1028 case 'E':
1029 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
1030 count += count_occurrences (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), find, count_dest);
1031 break;
1032 }
1033 }
1034 return count;
1035}
1036
1037
1038/* Return TRUE if OP is a register or subreg of a register that
1039 holds an unsigned quantity. Otherwise, return FALSE. */
1040
1041bool
1042unsigned_reg_p (rtx op)
1043{
1044 if (REG_P (op)(((enum rtx_code) (op)->code) == REG)
1045 && REG_EXPR (op)(((&(op)->u.reg)->attrs) == 0 ? 0 : ((&(op)->
u.reg)->attrs)->decl)
1046 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op)))((tree_class_check ((((contains_struct_check (((((&(op)->
u.reg)->attrs) == 0 ? 0 : ((&(op)->u.reg)->attrs
)->decl)), (TS_TYPED), "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 1046, __FUNCTION__))->typed.type)), (tcc_type), "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 1046, __FUNCTION__))->base.u.bits.unsigned_flag)
)
1047 return true;
1048
1049 if (GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG
1050 && SUBREG_PROMOTED_SIGN (op)((__extension__ ({ __typeof ((op)) const _rtx = ((op)); if ((
(enum rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag
("SUBREG_PROMOTED_SIGN", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 1050, __FUNCTION__); _rtx; })->volatil) ? 1 : (op)->unchanging
- 1)
)
1051 return true;
1052
1053 return false;
1054}
1055
1056
1057/* Nonzero if register REG appears somewhere within IN.
1058 Also works if REG is not a register; in this case it checks
1059 for a subexpression of IN that is Lisp "equal" to REG. */
1060
1061int
1062reg_mentioned_p (const_rtx reg, const_rtx in)
1063{
1064 const char *fmt;
1065 int i;
1066 enum rtx_code code;
1067
1068 if (in == 0)
1069 return 0;
1070
1071 if (reg == in)
1072 return 1;
1073
1074 if (GET_CODE (in)((enum rtx_code) (in)->code) == LABEL_REF)
1075 return reg == label_ref_label (in);
1076
1077 code = GET_CODE (in)((enum rtx_code) (in)->code);
1078
1079 switch (code)
1080 {
1081 /* Compare registers by number. */
1082 case REG:
1083 return REG_P (reg)(((enum rtx_code) (reg)->code) == REG) && REGNO (in)(rhs_regno(in)) == REGNO (reg)(rhs_regno(reg));
1084
1085 /* These codes have no constituent expressions
1086 and are unique. */
1087 case SCRATCH:
1088 case CC0:
1089 case PC:
1090 return 0;
1091
1092 CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR
:
1093 /* These are kept unique for a given value. */
1094 return 0;
1095
1096 default:
1097 break;
1098 }
1099
1100 if (GET_CODE (reg)((enum rtx_code) (reg)->code) == code && rtx_equal_p (reg, in))
1101 return 1;
1102
1103 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
1104
1105 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
1106 {
1107 if (fmt[i] == 'E')
1108 {
1109 int j;
1110 for (j = XVECLEN (in, i)(((((in)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
1111 if (reg_mentioned_p (reg, XVECEXP (in, i, j)(((((in)->u.fld[i]).rt_rtvec))->elem[j])))
1112 return 1;
1113 }
1114 else if (fmt[i] == 'e'
1115 && reg_mentioned_p (reg, XEXP (in, i)(((in)->u.fld[i]).rt_rtx)))
1116 return 1;
1117 }
1118 return 0;
1119}
1120
1121/* Return 1 if in between BEG and END, exclusive of BEG and END, there is
1122 no CODE_LABEL insn. */
1123
1124int
1125no_labels_between_p (const rtx_insn *beg, const rtx_insn *end)
1126{
1127 rtx_insn *p;
1128 if (beg == end)
1129 return 0;
1130 for (p = NEXT_INSN (beg); p != end; p = NEXT_INSN (p))
1131 if (LABEL_P (p)(((enum rtx_code) (p)->code) == CODE_LABEL))
1132 return 0;
1133 return 1;
1134}
1135
1136/* Nonzero if register REG is used in an insn between
1137 FROM_INSN and TO_INSN (exclusive of those two). */
1138
1139int
1140reg_used_between_p (const_rtx reg, const rtx_insn *from_insn,
1141 const rtx_insn *to_insn)
1142{
1143 rtx_insn *insn;
1144
1145 if (from_insn == to_insn)
1146 return 0;
1147
1148 for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn))
1149 if (NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN))
1150 && (reg_overlap_mentioned_p (reg, PATTERN (insn))
1151 || (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN) && find_reg_fusage (insn, USE, reg))))
1152 return 1;
1153 return 0;
1154}
1155
1156/* Nonzero if the old value of X, a register, is referenced in BODY. If X
1157 is entirely replaced by a new value and the only use is as a SET_DEST,
1158 we do not consider it a reference. */
1159
1160int
1161reg_referenced_p (const_rtx x, const_rtx body)
1162{
1163 int i;
1164
1165 switch (GET_CODE (body)((enum rtx_code) (body)->code))
1166 {
1167 case SET:
1168 if (reg_overlap_mentioned_p (x, SET_SRC (body)(((body)->u.fld[1]).rt_rtx)))
1169 return 1;
1170
1171 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
1172 of a REG that occupies all of the REG, the insn references X if
1173 it is mentioned in the destination. */
1174 if (GET_CODE (SET_DEST (body))((enum rtx_code) ((((body)->u.fld[0]).rt_rtx))->code) != CC0
1175 && GET_CODE (SET_DEST (body))((enum rtx_code) ((((body)->u.fld[0]).rt_rtx))->code) != PC
1176 && !REG_P (SET_DEST (body))(((enum rtx_code) ((((body)->u.fld[0]).rt_rtx))->code) ==
REG)
1177 && ! (GET_CODE (SET_DEST (body))((enum rtx_code) ((((body)->u.fld[0]).rt_rtx))->code) == SUBREG
1178 && REG_P (SUBREG_REG (SET_DEST (body)))(((enum rtx_code) (((((((body)->u.fld[0]).rt_rtx))->u.fld
[0]).rt_rtx))->code) == REG)
1179 && !read_modify_subreg_p (SET_DEST (body)(((body)->u.fld[0]).rt_rtx)))
1180 && reg_overlap_mentioned_p (x, SET_DEST (body)(((body)->u.fld[0]).rt_rtx)))
1181 return 1;
1182 return 0;
1183
1184 case ASM_OPERANDS:
1185 for (i = ASM_OPERANDS_INPUT_LENGTH (body)(((((body)->u.fld[3]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
1186 if (reg_overlap_mentioned_p (x, ASM_OPERANDS_INPUT (body, i)(((((body)->u.fld[3]).rt_rtvec))->elem[i])))
1187 return 1;
1188 return 0;
1189
1190 case CALL:
1191 case USE:
1192 case IF_THEN_ELSE:
1193 return reg_overlap_mentioned_p (x, body);
1194
1195 case TRAP_IF:
1196 return reg_overlap_mentioned_p (x, TRAP_CONDITION (body)(((body)->u.fld[0]).rt_rtx));
1197
1198 case PREFETCH:
1199 return reg_overlap_mentioned_p (x, XEXP (body, 0)(((body)->u.fld[0]).rt_rtx));
1200
1201 case UNSPEC:
1202 case UNSPEC_VOLATILE:
1203 for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
1204 if (reg_overlap_mentioned_p (x, XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i])))
1205 return 1;
1206 return 0;
1207
1208 case PARALLEL:
1209 for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
1210 if (reg_referenced_p (x, XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i])))
1211 return 1;
1212 return 0;
1213
1214 case CLOBBER:
1215 if (MEM_P (XEXP (body, 0))(((enum rtx_code) ((((body)->u.fld[0]).rt_rtx))->code) ==
MEM)
)
1216 if (reg_overlap_mentioned_p (x, XEXP (XEXP (body, 0), 0)((((((body)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx)))
1217 return 1;
1218 return 0;
1219
1220 case COND_EXEC:
1221 if (reg_overlap_mentioned_p (x, COND_EXEC_TEST (body)(((body)->u.fld[0]).rt_rtx)))
1222 return 1;
1223 return reg_referenced_p (x, COND_EXEC_CODE (body)(((body)->u.fld[1]).rt_rtx));
1224
1225 default:
1226 return 0;
1227 }
1228}
1229
1230/* Nonzero if register REG is set or clobbered in an insn between
1231 FROM_INSN and TO_INSN (exclusive of those two). */
1232
1233int
1234reg_set_between_p (const_rtx reg, const rtx_insn *from_insn,
1235 const rtx_insn *to_insn)
1236{
1237 const rtx_insn *insn;
1238
1239 if (from_insn == to_insn)
1240 return 0;
1241
1242 for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn))
1243 if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
&& reg_set_p (reg, insn))
1244 return 1;
1245 return 0;
1246}
1247
1248/* Return true if REG is set or clobbered inside INSN. */
1249
1250int
1251reg_set_p (const_rtx reg, const_rtx insn)
1252{
1253 /* After delay slot handling, call and branch insns might be in a
1254 sequence. Check all the elements there. */
1255 if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
&& GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == SEQUENCE)
1256 {
1257 for (int i = 0; i < XVECLEN (PATTERN (insn), 0)(((((PATTERN (insn))->u.fld[0]).rt_rtvec))->num_elem); ++i)
1258 if (reg_set_p (reg, XVECEXP (PATTERN (insn), 0, i)(((((PATTERN (insn))->u.fld[0]).rt_rtvec))->elem[i])))
1259 return true;
1260
1261 return false;
1262 }
1263
1264 /* We can be passed an insn or part of one. If we are passed an insn,
1265 check if a side-effect of the insn clobbers REG. */
1266 if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
1267 && (FIND_REG_INC_NOTE (insn, reg)0
1268 || (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN)
1269 && ((REG_P (reg)(((enum rtx_code) (reg)->code) == REG)
1270 && REGNO (reg)(rhs_regno(reg)) < FIRST_PSEUDO_REGISTER76
1271 && (insn_callee_abi (as_a<const rtx_insn *> (insn))
1272 .clobbers_reg_p (GET_MODE (reg)((machine_mode) (reg)->mode), REGNO (reg)(rhs_regno(reg)))))
1273 || MEM_P (reg)(((enum rtx_code) (reg)->code) == MEM)
1274 || find_reg_fusage (insn, CLOBBER, reg)))))
1275 return true;
1276
1277 /* There are no REG_INC notes for SP autoinc. */
1278 if (reg == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]) && INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
)
1279 {
1280 subrtx_var_iterator::array_type array;
1281 FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (insn), NONCONST)for (subrtx_var_iterator iter (array, PATTERN (insn), rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
1282 {
1283 rtx mem = *iter;
1284 if (mem
1285 && MEM_P (mem)(((enum rtx_code) (mem)->code) == MEM)
1286 && GET_RTX_CLASS (GET_CODE (XEXP (mem, 0)))(rtx_class[(int) (((enum rtx_code) ((((mem)->u.fld[0]).rt_rtx
))->code))])
== RTX_AUTOINC)
1287 {
1288 if (XEXP (XEXP (mem, 0), 0)((((((mem)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
1289 return true;
1290 iter.skip_subrtxes ();
1291 }
1292 }
1293 }
1294
1295 return set_of (reg, insn) != NULL_RTX(rtx) 0;
1296}
1297
1298/* Similar to reg_set_between_p, but check all registers in X. Return 0
1299 only if none of them are modified between START and END. Return 1 if
1300 X contains a MEM; this routine does use memory aliasing. */
1301
1302int
1303modified_between_p (const_rtx x, const rtx_insn *start, const rtx_insn *end)
1304{
1305 const enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
1306 const char *fmt;
1307 int i, j;
1308 rtx_insn *insn;
1309
1310 if (start == end)
1311 return 0;
1312
1313 switch (code)
1314 {
1315 CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR
:
1316 case CONST:
1317 case SYMBOL_REF:
1318 case LABEL_REF:
1319 return 0;
1320
1321 case PC:
1322 case CC0:
1323 return 1;
1324
1325 case MEM:
1326 if (modified_between_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), start, end))
1327 return 1;
1328 if (MEM_READONLY_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 1328, __FUNCTION__); _rtx; })->unchanging)
)
1329 return 0;
1330 for (insn = NEXT_INSN (start); insn != end; insn = NEXT_INSN (insn))
1331 if (memory_modified_in_insn_p (x, insn))
1332 return 1;
1333 return 0;
1334
1335 case REG:
1336 return reg_set_between_p (x, start, end);
1337
1338 default:
1339 break;
1340 }
1341
1342 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
1343 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
1344 {
1345 if (fmt[i] == 'e' && modified_between_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), start, end))
1346 return 1;
1347
1348 else if (fmt[i] == 'E')
1349 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
1350 if (modified_between_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), start, end))
1351 return 1;
1352 }
1353
1354 return 0;
1355}
1356
1357/* Similar to reg_set_p, but check all registers in X. Return 0 only if none
1358 of them are modified in INSN. Return 1 if X contains a MEM; this routine
1359 does use memory aliasing. */
1360
1361int
1362modified_in_p (const_rtx x, const_rtx insn)
1363{
1364 const enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
1365 const char *fmt;
1366 int i, j;
1367
1368 switch (code)
1369 {
1370 CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR
:
1371 case CONST:
1372 case SYMBOL_REF:
1373 case LABEL_REF:
1374 return 0;
1375
1376 case PC:
1377 case CC0:
1378 return 1;
1379
1380 case MEM:
1381 if (modified_in_p (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), insn))
1382 return 1;
1383 if (MEM_READONLY_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 1383, __FUNCTION__); _rtx; })->unchanging)
)
1384 return 0;
1385 if (memory_modified_in_insn_p (x, insn))
1386 return 1;
1387 return 0;
1388
1389 case REG:
1390 return reg_set_p (x, insn);
1391
1392 default:
1393 break;
1394 }
1395
1396 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
1397 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
1398 {
1399 if (fmt[i] == 'e' && modified_in_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), insn))
1400 return 1;
1401
1402 else if (fmt[i] == 'E')
1403 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
1404 if (modified_in_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), insn))
1405 return 1;
1406 }
1407
1408 return 0;
1409}
1410
1411/* Return true if X is a SUBREG and if storing a value to X would
1412 preserve some of its SUBREG_REG. For example, on a normal 32-bit
1413 target, using a SUBREG to store to one half of a DImode REG would
1414 preserve the other half. */
1415
1416bool
1417read_modify_subreg_p (const_rtx x)
1418{
1419 if (GET_CODE (x)((enum rtx_code) (x)->code) != SUBREG)
1420 return false;
1421 poly_uint64 isize = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode));
1422 poly_uint64 osize = GET_MODE_SIZE (GET_MODE (x)((machine_mode) (x)->mode));
1423 poly_uint64 regsize = REGMODE_NATURAL_SIZE (GET_MODE (SUBREG_REG (x)))ix86_regmode_natural_size (((machine_mode) ((((x)->u.fld[0
]).rt_rtx))->mode))
;
1424 /* The inner and outer modes of a subreg must be ordered, so that we
1425 can tell whether they're paradoxical or partial. */
1426 gcc_checking_assert (ordered_p (isize, osize))((void)(!(ordered_p (isize, osize)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 1426, __FUNCTION__), 0 : 0))
;
1427 return (maybe_gt (isize, osize)maybe_lt (osize, isize) && maybe_gt (isize, regsize)maybe_lt (regsize, isize));
1428}
1429
1430/* Helper function for set_of. */
1431struct set_of_data
1432 {
1433 const_rtx found;
1434 const_rtx pat;
1435 };
1436
1437static void
1438set_of_1 (rtx x, const_rtx pat, void *data1)
1439{
1440 struct set_of_data *const data = (struct set_of_data *) (data1);
1441 if (rtx_equal_p (x, data->pat)
1442 || (!MEM_P (x)(((enum rtx_code) (x)->code) == MEM) && reg_overlap_mentioned_p (data->pat, x)))
1443 data->found = pat;
1444}
1445
1446/* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1447 (either directly or via STRICT_LOW_PART and similar modifiers). */
1448const_rtx
1449set_of (const_rtx pat, const_rtx insn)
1450{
1451 struct set_of_data data;
1452 data.found = NULL_RTX(rtx) 0;
1453 data.pat = pat;
1454 note_pattern_stores (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
? PATTERN (insn) : insn, set_of_1, &data);
1455 return data.found;
1456}
1457
1458/* Check whether instruction pattern PAT contains a SET with the following
1459 properties:
1460
1461 - the SET is executed unconditionally; and
1462 - either:
1463 - the destination of the SET is a REG that contains REGNO; or
1464 - both:
1465 - the destination of the SET is a SUBREG of such a REG; and
1466 - writing to the subreg clobbers all of the SUBREG_REG
1467 (in other words, read_modify_subreg_p is false).
1468
1469 If PAT does have a SET like that, return the set, otherwise return null.
1470
1471 This is intended to be an alternative to single_set for passes that
1472 can handle patterns with multiple_sets. */
1473rtx
1474simple_regno_set (rtx pat, unsigned int regno)
1475{
1476 if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL)
1477 {
1478 int last = XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem) - 1;
1479 for (int i = 0; i < last; ++i)
1480 if (rtx set = simple_regno_set (XVECEXP (pat, 0, i)(((((pat)->u.fld[0]).rt_rtvec))->elem[i]), regno))
1481 return set;
1482
1483 pat = XVECEXP (pat, 0, last)(((((pat)->u.fld[0]).rt_rtvec))->elem[last]);
1484 }
1485
1486 if (GET_CODE (pat)((enum rtx_code) (pat)->code) == SET
1487 && covers_regno_no_parallel_p (SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx), regno))
1488 return pat;
1489
1490 return nullptr;
1491}
1492
1493/* Add all hard register in X to *PSET. */
1494void
1495find_all_hard_regs (const_rtx x, HARD_REG_SET *pset)
1496{
1497 subrtx_iterator::array_type array;
1498 FOR_EACH_SUBRTX (iter, array, x, NONCONST)for (subrtx_iterator iter (array, x, rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
1499 {
1500 const_rtx x = *iter;
1501 if (REG_P (x)(((enum rtx_code) (x)->code) == REG) && REGNO (x)(rhs_regno(x)) < FIRST_PSEUDO_REGISTER76)
1502 add_to_hard_reg_set (pset, GET_MODE (x)((machine_mode) (x)->mode), REGNO (x)(rhs_regno(x)));
1503 }
1504}
1505
1506/* This function, called through note_stores, collects sets and
1507 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1508 by DATA. */
1509void
1510record_hard_reg_sets (rtx x, const_rtx pat ATTRIBUTE_UNUSED__attribute__ ((__unused__)), void *data)
1511{
1512 HARD_REG_SET *pset = (HARD_REG_SET *)data;
1513 if (REG_P (x)(((enum rtx_code) (x)->code) == REG) && HARD_REGISTER_P (x)((((rhs_regno(x))) < 76)))
1514 add_to_hard_reg_set (pset, GET_MODE (x)((machine_mode) (x)->mode), REGNO (x)(rhs_regno(x)));
1515}
1516
1517/* Examine INSN, and compute the set of hard registers written by it.
1518 Store it in *PSET. Should only be called after reload.
1519
1520 IMPLICIT is true if we should include registers that are fully-clobbered
1521 by calls. This should be used with caution, since it doesn't include
1522 partially-clobbered registers. */
1523void
1524find_all_hard_reg_sets (const rtx_insn *insn, HARD_REG_SET *pset, bool implicit)
1525{
1526 rtx link;
1527
1528 CLEAR_HARD_REG_SET (*pset);
1529 note_stores (insn, record_hard_reg_sets, pset);
1530 if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN) && implicit)
1531 *pset |= insn_callee_abi (insn).full_reg_clobbers ();
1532 for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
1533 if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == REG_INC)
1534 record_hard_reg_sets (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), NULLnullptr, pset);
1535}
1536
1537/* Like record_hard_reg_sets, but called through note_uses. */
1538void
1539record_hard_reg_uses (rtx *px, void *data)
1540{
1541 find_all_hard_regs (*px, (HARD_REG_SET *) data);
1542}
1543
1544/* Given an INSN, return a SET expression if this insn has only a single SET.
1545 It may also have CLOBBERs, USEs, or SET whose output
1546 will not be used, which we ignore. */
1547
1548rtx
1549single_set_2 (const rtx_insn *insn, const_rtx pat)
1550{
1551 rtx set = NULLnullptr;
1552 int set_verified = 1;
1553 int i;
1554
1555 if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL)
1556 {
1557 for (i = 0; i < XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
1558 {
1559 rtx sub = XVECEXP (pat, 0, i)(((((pat)->u.fld[0]).rt_rtvec))->elem[i]);
1560 switch (GET_CODE (sub)((enum rtx_code) (sub)->code))
1561 {
1562 case USE:
1563 case CLOBBER:
1564 break;
1565
1566 case SET:
1567 /* We can consider insns having multiple sets, where all
1568 but one are dead as single set insns. In common case
1569 only single set is present in the pattern so we want
1570 to avoid checking for REG_UNUSED notes unless necessary.
1571
1572 When we reach set first time, we just expect this is
1573 the single set we are looking for and only when more
1574 sets are found in the insn, we check them. */
1575 if (!set_verified)
1576 {
1577 if (find_reg_note (insn, REG_UNUSED, SET_DEST (set)(((set)->u.fld[0]).rt_rtx))
1578 && !side_effects_p (set))
1579 set = NULLnullptr;
1580 else
1581 set_verified = 1;
1582 }
1583 if (!set)
1584 set = sub, set_verified = 0;
1585 else if (!find_reg_note (insn, REG_UNUSED, SET_DEST (sub)(((sub)->u.fld[0]).rt_rtx))
1586 || side_effects_p (sub))
1587 return NULL_RTX(rtx) 0;
1588 break;
1589
1590 default:
1591 return NULL_RTX(rtx) 0;
1592 }
1593 }
1594 }
1595 return set;
1596}
1597
1598/* Given an INSN, return nonzero if it has more than one SET, else return
1599 zero. */
1600
1601int
1602multiple_sets (const_rtx insn)
1603{
1604 int found;
1605 int i;
1606
1607 /* INSN must be an insn. */
1608 if (! INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
)
1609 return 0;
1610
1611 /* Only a PARALLEL can have multiple SETs. */
1612 if (GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == PARALLEL)
1613 {
1614 for (i = 0, found = 0; i < XVECLEN (PATTERN (insn), 0)(((((PATTERN (insn))->u.fld[0]).rt_rtvec))->num_elem); i++)
1615 if (GET_CODE (XVECEXP (PATTERN (insn), 0, i))((enum rtx_code) ((((((PATTERN (insn))->u.fld[0]).rt_rtvec
))->elem[i]))->code)
== SET)
1616 {
1617 /* If we have already found a SET, then return now. */
1618 if (found)
1619 return 1;
1620 else
1621 found = 1;
1622 }
1623 }
1624
1625 /* Either zero or one SET. */
1626 return 0;
1627}
1628
1629/* Return nonzero if the destination of SET equals the source
1630 and there are no side effects. */
1631
1632int
1633set_noop_p (const_rtx set)
1634{
1635 rtx src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
1636 rtx dst = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);
1637
1638 if (dst == pc_rtx && src == pc_rtx)
1639 return 1;
1640
1641 if (MEM_P (dst)(((enum rtx_code) (dst)->code) == MEM) && MEM_P (src)(((enum rtx_code) (src)->code) == MEM))
1642 return rtx_equal_p (dst, src) && !side_effects_p (dst);
1643
1644 if (GET_CODE (dst)((enum rtx_code) (dst)->code) == ZERO_EXTRACT)
1645 return rtx_equal_p (XEXP (dst, 0)(((dst)->u.fld[0]).rt_rtx), src)
1646 && !BITS_BIG_ENDIAN0 && XEXP (dst, 2)(((dst)->u.fld[2]).rt_rtx) == const0_rtx(const_int_rtx[64])
1647 && !side_effects_p (src);
1648
1649 if (GET_CODE (dst)((enum rtx_code) (dst)->code) == STRICT_LOW_PART)
1650 dst = XEXP (dst, 0)(((dst)->u.fld[0]).rt_rtx);
1651
1652 if (GET_CODE (src)((enum rtx_code) (src)->code) == SUBREG && GET_CODE (dst)((enum rtx_code) (dst)->code) == SUBREG)
1653 {
1654 if (maybe_ne (SUBREG_BYTE (src)(((src)->u.fld[1]).rt_subreg), SUBREG_BYTE (dst)(((dst)->u.fld[1]).rt_subreg)))
1655 return 0;
1656 src = SUBREG_REG (src)(((src)->u.fld[0]).rt_rtx);
1657 dst = SUBREG_REG (dst)(((dst)->u.fld[0]).rt_rtx);
1658 if (GET_MODE (src)((machine_mode) (src)->mode) != GET_MODE (dst)((machine_mode) (dst)->mode))
1659 /* It is hard to tell whether subregs refer to the same bits, so act
1660 conservatively and return 0. */
1661 return 0;
1662 }
1663
1664 /* It is a NOOP if destination overlaps with selected src vector
1665 elements. */
1666 if (GET_CODE (src)((enum rtx_code) (src)->code) == VEC_SELECT
1667 && REG_P (XEXP (src, 0))(((enum rtx_code) ((((src)->u.fld[0]).rt_rtx))->code) ==
REG)
&& REG_P (dst)(((enum rtx_code) (dst)->code) == REG)
1668 && HARD_REGISTER_P (XEXP (src, 0))((((rhs_regno((((src)->u.fld[0]).rt_rtx)))) < 76))
1669 && HARD_REGISTER_P (dst)((((rhs_regno(dst))) < 76)))
1670 {
1671 int i;
1672 rtx par = XEXP (src, 1)(((src)->u.fld[1]).rt_rtx);
1673 rtx src0 = XEXP (src, 0)(((src)->u.fld[0]).rt_rtx);
1674 poly_int64 c0;
1675 if (!poly_int_rtx_p (XVECEXP (par, 0, 0)(((((par)->u.fld[0]).rt_rtvec))->elem[0]), &c0))
1676 return 0;
1677 poly_int64 offset = GET_MODE_UNIT_SIZE (GET_MODE (src0))mode_to_unit_size (((machine_mode) (src0)->mode)) * c0;
1678
1679 for (i = 1; i < XVECLEN (par, 0)(((((par)->u.fld[0]).rt_rtvec))->num_elem); i++)
1680 {
1681 poly_int64 c0i;
1682 if (!poly_int_rtx_p (XVECEXP (par, 0, i)(((((par)->u.fld[0]).rt_rtvec))->elem[i]), &c0i)
1683 || maybe_ne (c0i, c0 + i))
1684 return 0;
1685 }
1686 return
1687 REG_CAN_CHANGE_MODE_P (REGNO (dst), GET_MODE (src0), GET_MODE (dst))(targetm.can_change_mode_class (((machine_mode) (src0)->mode
), ((machine_mode) (dst)->mode), (regclass_map[((rhs_regno
(dst)))])))
1688 && simplify_subreg_regno (REGNO (src0)(rhs_regno(src0)), GET_MODE (src0)((machine_mode) (src0)->mode),
1689 offset, GET_MODE (dst)((machine_mode) (dst)->mode)) == (int) REGNO (dst)(rhs_regno(dst));
1690 }
1691
1692 return (REG_P (src)(((enum rtx_code) (src)->code) == REG) && REG_P (dst)(((enum rtx_code) (dst)->code) == REG)
1693 && REGNO (src)(rhs_regno(src)) == REGNO (dst)(rhs_regno(dst)));
1694}
1695
1696/* Return nonzero if an insn consists only of SETs, each of which only sets a
1697 value to itself. */
1698
1699int
1700noop_move_p (const rtx_insn *insn)
1701{
1702 rtx pat = PATTERN (insn);
1703
1704 if (INSN_CODE (insn)(((insn)->u.fld[5]).rt_int) == NOOP_MOVE_INSN_CODE2147483647)
1705 return 1;
1706
1707 /* Check the code to be executed for COND_EXEC. */
1708 if (GET_CODE (pat)((enum rtx_code) (pat)->code) == COND_EXEC)
1709 pat = COND_EXEC_CODE (pat)(((pat)->u.fld[1]).rt_rtx);
1710
1711 if (GET_CODE (pat)((enum rtx_code) (pat)->code) == SET && set_noop_p (pat))
1712 return 1;
1713
1714 if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL)
1715 {
1716 int i;
1717 /* If nothing but SETs of registers to themselves,
1718 this insn can also be deleted. */
1719 for (i = 0; i < XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem); i++)
1720 {
1721 rtx tem = XVECEXP (pat, 0, i)(((((pat)->u.fld[0]).rt_rtvec))->elem[i]);
1722
1723 if (GET_CODE (tem)((enum rtx_code) (tem)->code) == USE || GET_CODE (tem)((enum rtx_code) (tem)->code) == CLOBBER)
1724 continue;
1725
1726 if (GET_CODE (tem)((enum rtx_code) (tem)->code) != SET || ! set_noop_p (tem))
1727 return 0;
1728 }
1729
1730 return 1;
1731 }
1732 return 0;
1733}
1734
1735
1736/* Return nonzero if register in range [REGNO, ENDREGNO)
1737 appears either explicitly or implicitly in X
1738 other than being stored into.
1739
1740 References contained within the substructure at LOC do not count.
1741 LOC may be zero, meaning don't ignore anything. */
1742
1743bool
1744refers_to_regno_p (unsigned int regno, unsigned int endregno, const_rtx x,
1745 rtx *loc)
1746{
1747 int i;
1748 unsigned int x_regno;
1749 RTX_CODEenum rtx_code code;
1750 const char *fmt;
1751
1752 repeat:
1753 /* The contents of a REG_NONNEG note is always zero, so we must come here
1754 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1755 if (x == 0)
1756 return false;
1757
1758 code = GET_CODE (x)((enum rtx_code) (x)->code);
1759
1760 switch (code)
1761 {
1762 case REG:
1763 x_regno = REGNO (x)(rhs_regno(x));
1764
1765 /* If we modifying the stack, frame, or argument pointer, it will
1766 clobber a virtual register. In fact, we could be more precise,
1767 but it isn't worth it. */
1768 if ((x_regno == STACK_POINTER_REGNUM7
1769 || (FRAME_POINTER_REGNUM19 != ARG_POINTER_REGNUM16
1770 && x_regno == ARG_POINTER_REGNUM16)
1771 || x_regno == FRAME_POINTER_REGNUM19)
1772 && regno >= FIRST_VIRTUAL_REGISTER(76) && regno <= LAST_VIRTUAL_REGISTER(((76)) + 5))
1773 return true;
1774
1775 return endregno > x_regno && regno < END_REGNO (x);
1776
1777 case SUBREG:
1778 /* If this is a SUBREG of a hard reg, we can see exactly which
1779 registers are being modified. Otherwise, handle normally. */
1780 if (REG_P (SUBREG_REG (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
1781 && REGNO (SUBREG_REG (x))(rhs_regno((((x)->u.fld[0]).rt_rtx))) < FIRST_PSEUDO_REGISTER76)
1782 {
1783 unsigned int inner_regno = subreg_regno (x);
1784 unsigned int inner_endregno
1785 = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER76
1786 ? subreg_nregs (x) : 1);
1787
1788 return endregno > inner_regno && regno < inner_endregno;
1789 }
1790 break;
1791
1792 case CLOBBER:
1793 case SET:
1794 if (&SET_DEST (x)(((x)->u.fld[0]).rt_rtx) != loc
1795 /* Note setting a SUBREG counts as referring to the REG it is in for
1796 a pseudo but not for hard registers since we can
1797 treat each word individually. */
1798 && ((GET_CODE (SET_DEST (x))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == SUBREG
1799 && loc != &SUBREG_REG (SET_DEST (x))((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx)
1800 && REG_P (SUBREG_REG (SET_DEST (x)))(((enum rtx_code) (((((((x)->u.fld[0]).rt_rtx))->u.fld[
0]).rt_rtx))->code) == REG)
1801 && REGNO (SUBREG_REG (SET_DEST (x)))(rhs_regno(((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx
)))
>= FIRST_PSEUDO_REGISTER76
1802 && refers_to_regno_p (regno, endregno,
1803 SUBREG_REG (SET_DEST (x))((((((x)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx), loc))
1804 || (!REG_P (SET_DEST (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == REG
)
1805 && refers_to_regno_p (regno, endregno, SET_DEST (x)(((x)->u.fld[0]).rt_rtx), loc))))
1806 return true;
1807
1808 if (code == CLOBBER || loc == &SET_SRC (x)(((x)->u.fld[1]).rt_rtx))
1809 return false;
1810 x = SET_SRC (x)(((x)->u.fld[1]).rt_rtx);
1811 goto repeat;
1812
1813 default:
1814 break;
1815 }
1816
1817 /* X does not match, so try its subexpressions. */
1818
1819 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
1820 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
1821 {
1822 if (fmt[i] == 'e' && loc != &XEXP (x, i)(((x)->u.fld[i]).rt_rtx))
1823 {
1824 if (i == 0)
1825 {
1826 x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
1827 goto repeat;
1828 }
1829 else
1830 if (refers_to_regno_p (regno, endregno, XEXP (x, i)(((x)->u.fld[i]).rt_rtx), loc))
1831 return true;
1832 }
1833 else if (fmt[i] == 'E')
1834 {
1835 int j;
1836 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
1837 if (loc != &XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])
1838 && refers_to_regno_p (regno, endregno, XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), loc))
1839 return true;
1840 }
1841 }
1842 return false;
1843}
1844
1845/* Nonzero if modifying X will affect IN. If X is a register or a SUBREG,
1846 we check if any register number in X conflicts with the relevant register
1847 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN
1848 contains a MEM (we don't bother checking for memory addresses that can't
1849 conflict because we expect this to be a rare case. */
1850
1851int
1852reg_overlap_mentioned_p (const_rtx x, const_rtx in)
1853{
1854 unsigned int regno, endregno;
1855
1856 /* If either argument is a constant, then modifying X cannot
1857 affect IN. Here we look at IN, we can profitably combine
1858 CONSTANT_P (x) with the switch statement below. */
1859 if (CONSTANT_P (in)((rtx_class[(int) (((enum rtx_code) (in)->code))]) == RTX_CONST_OBJ
)
)
1860 return 0;
1861
1862 recurse:
1863 switch (GET_CODE (x)((enum rtx_code) (x)->code))
1864 {
1865 case CLOBBER:
1866 case STRICT_LOW_PART:
1867 case ZERO_EXTRACT:
1868 case SIGN_EXTRACT:
1869 /* Overly conservative. */
1870 x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
1871 goto recurse;
1872
1873 case SUBREG:
1874 regno = REGNO (SUBREG_REG (x))(rhs_regno((((x)->u.fld[0]).rt_rtx)));
1875 if (regno < FIRST_PSEUDO_REGISTER76)
1876 regno = subreg_regno (x);
1877 endregno = regno + (regno < FIRST_PSEUDO_REGISTER76
1878 ? subreg_nregs (x) : 1);
1879 goto do_reg;
1880
1881 case REG:
1882 regno = REGNO (x)(rhs_regno(x));
1883 endregno = END_REGNO (x);
1884 do_reg:
1885 return refers_to_regno_p (regno, endregno, in, (rtx*) 0);
1886
1887 case MEM:
1888 {
1889 const char *fmt;
1890 int i;
1891
1892 if (MEM_P (in)(((enum rtx_code) (in)->code) == MEM))
1893 return 1;
1894
1895 fmt = GET_RTX_FORMAT (GET_CODE (in))(rtx_format[(int) (((enum rtx_code) (in)->code))]);
1896 for (i = GET_RTX_LENGTH (GET_CODE (in))(rtx_length[(int) (((enum rtx_code) (in)->code))]) - 1; i >= 0; i--)
1897 if (fmt[i] == 'e')
1898 {
1899 if (reg_overlap_mentioned_p (x, XEXP (in, i)(((in)->u.fld[i]).rt_rtx)))
1900 return 1;
1901 }
1902 else if (fmt[i] == 'E')
1903 {
1904 int j;
1905 for (j = XVECLEN (in, i)(((((in)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; --j)
1906 if (reg_overlap_mentioned_p (x, XVECEXP (in, i, j)(((((in)->u.fld[i]).rt_rtvec))->elem[j])))
1907 return 1;
1908 }
1909
1910 return 0;
1911 }
1912
1913 case SCRATCH:
1914 case PC:
1915 case CC0:
1916 return reg_mentioned_p (x, in);
1917
1918 case PARALLEL:
1919 {
1920 int i;
1921
1922 /* If any register in here refers to it we return true. */
1923 for (i = XVECLEN (x, 0)(((((x)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
1924 if (XEXP (XVECEXP (x, 0, i), 0)((((((((x)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld[0
]).rt_rtx)
!= 0
1925 && reg_overlap_mentioned_p (XEXP (XVECEXP (x, 0, i), 0)((((((((x)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld[0
]).rt_rtx)
, in))
1926 return 1;
1927 return 0;
1928 }
1929
1930 default:
1931 gcc_assert (CONSTANT_P (x))((void)(!(((rtx_class[(int) (((enum rtx_code) (x)->code))]
) == RTX_CONST_OBJ)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 1931, __FUNCTION__), 0 : 0))
;
1932 return 0;
1933 }
1934}
1935
1936/* Call FUN on each register or MEM that is stored into or clobbered by X.
1937 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1938 ignored by note_stores, but passed to FUN.
1939
1940 FUN receives three arguments:
1941 1. the REG, MEM, CC0 or PC being stored in or clobbered,
1942 2. the SET or CLOBBER rtx that does the store,
1943 3. the pointer DATA provided to note_stores.
1944
1945 If the item being stored in or clobbered is a SUBREG of a hard register,
1946 the SUBREG will be passed. */
1947
1948void
1949note_pattern_stores (const_rtx x,
1950 void (*fun) (rtx, const_rtx, void *), void *data)
1951{
1952 int i;
1953
1954 if (GET_CODE (x)((enum rtx_code) (x)->code) == COND_EXEC)
1955 x = COND_EXEC_CODE (x)(((x)->u.fld[1]).rt_rtx);
1956
1957 if (GET_CODE (x)((enum rtx_code) (x)->code) == SET || GET_CODE (x)((enum rtx_code) (x)->code) == CLOBBER)
1958 {
1959 rtx dest = SET_DEST (x)(((x)->u.fld[0]).rt_rtx);
1960
1961 while ((GET_CODE (dest)((enum rtx_code) (dest)->code) == SUBREG
1962 && (!REG_P (SUBREG_REG (dest))(((enum rtx_code) ((((dest)->u.fld[0]).rt_rtx))->code) ==
REG)
1963 || REGNO (SUBREG_REG (dest))(rhs_regno((((dest)->u.fld[0]).rt_rtx))) >= FIRST_PSEUDO_REGISTER76))
1964 || GET_CODE (dest)((enum rtx_code) (dest)->code) == ZERO_EXTRACT
1965 || GET_CODE (dest)((enum rtx_code) (dest)->code) == STRICT_LOW_PART)
1966 dest = XEXP (dest, 0)(((dest)->u.fld[0]).rt_rtx);
1967
1968 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1969 each of whose first operand is a register. */
1970 if (GET_CODE (dest)((enum rtx_code) (dest)->code) == PARALLEL)
1971 {
1972 for (i = XVECLEN (dest, 0)(((((dest)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
1973 if (XEXP (XVECEXP (dest, 0, i), 0)((((((((dest)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx)
!= 0)
1974 (*fun) (XEXP (XVECEXP (dest, 0, i), 0)((((((((dest)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx)
, x, data);
1975 }
1976 else
1977 (*fun) (dest, x, data);
1978 }
1979
1980 else if (GET_CODE (x)((enum rtx_code) (x)->code) == PARALLEL)
1981 for (i = XVECLEN (x, 0)(((((x)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
1982 note_pattern_stores (XVECEXP (x, 0, i)(((((x)->u.fld[0]).rt_rtvec))->elem[i]), fun, data);
1983}
1984
1985/* Same, but for an instruction. If the instruction is a call, include
1986 any CLOBBERs in its CALL_INSN_FUNCTION_USAGE. */
1987
1988void
1989note_stores (const rtx_insn *insn,
1990 void (*fun) (rtx, const_rtx, void *), void *data)
1991{
1992 if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
1993 for (rtx link = CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx);
1994 link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
1995 if (GET_CODE (XEXP (link, 0))((enum rtx_code) ((((link)->u.fld[0]).rt_rtx))->code) == CLOBBER)
1996 note_pattern_stores (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx), fun, data);
1997 note_pattern_stores (PATTERN (insn), fun, data);
1998}
1999
2000/* Like notes_stores, but call FUN for each expression that is being
2001 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
2002 FUN for each expression, not any interior subexpressions. FUN receives a
2003 pointer to the expression and the DATA passed to this function.
2004
2005 Note that this is not quite the same test as that done in reg_referenced_p
2006 since that considers something as being referenced if it is being
2007 partially set, while we do not. */
2008
2009void
2010note_uses (rtx *pbody, void (*fun) (rtx *, void *), void *data)
2011{
2012 rtx body = *pbody;
2013 int i;
2014
2015 switch (GET_CODE (body)((enum rtx_code) (body)->code))
2016 {
2017 case COND_EXEC:
2018 (*fun) (&COND_EXEC_TEST (body)(((body)->u.fld[0]).rt_rtx), data);
2019 note_uses (&COND_EXEC_CODE (body)(((body)->u.fld[1]).rt_rtx), fun, data);
2020 return;
2021
2022 case PARALLEL:
2023 for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
2024 note_uses (&XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i]), fun, data);
2025 return;
2026
2027 case SEQUENCE:
2028 for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
2029 note_uses (&PATTERN (XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i])), fun, data);
2030 return;
2031
2032 case USE:
2033 (*fun) (&XEXP (body, 0)(((body)->u.fld[0]).rt_rtx), data);
2034 return;
2035
2036 case ASM_OPERANDS:
2037 for (i = ASM_OPERANDS_INPUT_LENGTH (body)(((((body)->u.fld[3]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
2038 (*fun) (&ASM_OPERANDS_INPUT (body, i)(((((body)->u.fld[3]).rt_rtvec))->elem[i]), data);
2039 return;
2040
2041 case TRAP_IF:
2042 (*fun) (&TRAP_CONDITION (body)(((body)->u.fld[0]).rt_rtx), data);
2043 return;
2044
2045 case PREFETCH:
2046 (*fun) (&XEXP (body, 0)(((body)->u.fld[0]).rt_rtx), data);
2047 return;
2048
2049 case UNSPEC:
2050 case UNSPEC_VOLATILE:
2051 for (i = XVECLEN (body, 0)(((((body)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
2052 (*fun) (&XVECEXP (body, 0, i)(((((body)->u.fld[0]).rt_rtvec))->elem[i]), data);
2053 return;
2054
2055 case CLOBBER:
2056 if (MEM_P (XEXP (body, 0))(((enum rtx_code) ((((body)->u.fld[0]).rt_rtx))->code) ==
MEM)
)
2057 (*fun) (&XEXP (XEXP (body, 0), 0)((((((body)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx), data);
2058 return;
2059
2060 case SET:
2061 {
2062 rtx dest = SET_DEST (body)(((body)->u.fld[0]).rt_rtx);
2063
2064 /* For sets we replace everything in source plus registers in memory
2065 expression in store and operands of a ZERO_EXTRACT. */
2066 (*fun) (&SET_SRC (body)(((body)->u.fld[1]).rt_rtx), data);
2067
2068 if (GET_CODE (dest)((enum rtx_code) (dest)->code) == ZERO_EXTRACT)
2069 {
2070 (*fun) (&XEXP (dest, 1)(((dest)->u.fld[1]).rt_rtx), data);
2071 (*fun) (&XEXP (dest, 2)(((dest)->u.fld[2]).rt_rtx), data);
2072 }
2073
2074 while (GET_CODE (dest)((enum rtx_code) (dest)->code) == SUBREG || GET_CODE (dest)((enum rtx_code) (dest)->code) == STRICT_LOW_PART)
2075 dest = XEXP (dest, 0)(((dest)->u.fld[0]).rt_rtx);
2076
2077 if (MEM_P (dest)(((enum rtx_code) (dest)->code) == MEM))
2078 (*fun) (&XEXP (dest, 0)(((dest)->u.fld[0]).rt_rtx), data);
2079 }
2080 return;
2081
2082 default:
2083 /* All the other possibilities never store. */
2084 (*fun) (pbody, data);
2085 return;
2086 }
2087}
2088
2089/* Try to add a description of REG X to this object, stopping once
2090 the REF_END limit has been reached. FLAGS is a bitmask of
2091 rtx_obj_reference flags that describe the context. */
2092
2093void
2094rtx_properties::try_to_add_reg (const_rtx x, unsigned int flags)
2095{
2096 if (REG_NREGS (x)((&(x)->u.reg)->nregs) != 1)
2097 flags |= rtx_obj_flags::IS_MULTIREG;
2098 machine_mode mode = GET_MODE (x)((machine_mode) (x)->mode);
2099 unsigned int start_regno = REGNO (x)(rhs_regno(x));
2100 unsigned int end_regno = END_REGNO (x);
2101 for (unsigned int regno = start_regno; regno < end_regno; ++regno)
2102 if (ref_iter != ref_end)
2103 *ref_iter++ = rtx_obj_reference (regno, flags, mode,
2104 regno - start_regno);
2105}
2106
2107/* Add a description of destination X to this object. FLAGS is a bitmask
2108 of rtx_obj_reference flags that describe the context.
2109
2110 This routine accepts all rtxes that can legitimately appear in a
2111 SET_DEST. */
2112
2113void
2114rtx_properties::try_to_add_dest (const_rtx x, unsigned int flags)
2115{
2116 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
2117 each of whose first operand is a register. */
2118 if (__builtin_expect (GET_CODE (x)((enum rtx_code) (x)->code) == PARALLEL, 0))
2119 {
2120 for (int i = XVECLEN (x, 0)(((((x)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; --i)
2121 if (rtx dest = XEXP (XVECEXP (x, 0, i), 0)((((((((x)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld[0
]).rt_rtx)
)
2122 try_to_add_dest (dest, flags);
2123 return;
2124 }
2125
2126 unsigned int base_flags = flags & rtx_obj_flags::STICKY_FLAGS;
2127 flags |= rtx_obj_flags::IS_WRITE;
2128 for (;;)
2129 if (GET_CODE (x)((enum rtx_code) (x)->code) == ZERO_EXTRACT)
2130 {
2131 try_to_add_src (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), base_flags);
2132 try_to_add_src (XEXP (x, 2)(((x)->u.fld[2]).rt_rtx), base_flags);
2133 flags |= rtx_obj_flags::IS_READ;
2134 x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
2135 }
2136 else if (GET_CODE (x)((enum rtx_code) (x)->code) == STRICT_LOW_PART)
2137 {
2138 flags |= rtx_obj_flags::IS_READ;
2139 x = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
2140 }
2141 else if (GET_CODE (x)((enum rtx_code) (x)->code) == SUBREG)
2142 {
2143 flags |= rtx_obj_flags::IN_SUBREG;
2144 if (read_modify_subreg_p (x))
2145 flags |= rtx_obj_flags::IS_READ;
2146 x = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
2147 }
2148 else
2149 break;
2150
2151 if (MEM_P (x)(((enum rtx_code) (x)->code) == MEM))
2152 {
2153 if (ref_iter != ref_end)
2154 *ref_iter++ = rtx_obj_reference (MEM_REGNO, flags, GET_MODE (x)((machine_mode) (x)->mode));
2155
2156 unsigned int addr_flags = base_flags | rtx_obj_flags::IN_MEM_STORE;
2157 if (flags & rtx_obj_flags::IS_READ)
2158 addr_flags |= rtx_obj_flags::IN_MEM_LOAD;
2159 try_to_add_src (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), addr_flags);
2160 return;
2161 }
2162
2163 if (__builtin_expect (REG_P (x)(((enum rtx_code) (x)->code) == REG), 1))
2164 {
2165 /* We want to keep sp alive everywhere - by making all
2166 writes to sp also use sp. */
2167 if (REGNO (x)(rhs_regno(x)) == STACK_POINTER_REGNUM7)
2168 flags |= rtx_obj_flags::IS_READ;
2169 try_to_add_reg (x, flags);
2170 return;
2171 }
2172}
2173
2174/* Try to add a description of source X to this object, stopping once
2175 the REF_END limit has been reached. FLAGS is a bitmask of
2176 rtx_obj_reference flags that describe the context.
2177
2178 This routine accepts all rtxes that can legitimately appear in a SET_SRC. */
2179
2180void
2181rtx_properties::try_to_add_src (const_rtx x, unsigned int flags)
2182{
2183 unsigned int base_flags = flags & rtx_obj_flags::STICKY_FLAGS;
2184 subrtx_iterator::array_type array;
2185 FOR_EACH_SUBRTX (iter, array, x, NONCONST)for (subrtx_iterator iter (array, x, rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
2186 {
2187 const_rtx x = *iter;
2188 rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
2189 if (code == REG)
2190 try_to_add_reg (x, flags | rtx_obj_flags::IS_READ);
2191 else if (code == MEM)
2192 {
2193 if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2193, __FUNCTION__); _rtx; })->volatil)
)
2194 has_volatile_refs = true;
2195
2196 if (!MEM_READONLY_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_READONLY_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2196, __FUNCTION__); _rtx; })->unchanging)
&& ref_iter != ref_end)
2197 {
2198 auto mem_flags = flags | rtx_obj_flags::IS_READ;
2199 *ref_iter++ = rtx_obj_reference (MEM_REGNO, mem_flags,
2200 GET_MODE (x)((machine_mode) (x)->mode));
2201 }
2202
2203 try_to_add_src (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx),
2204 base_flags | rtx_obj_flags::IN_MEM_LOAD);
2205 iter.skip_subrtxes ();
2206 }
2207 else if (code == SUBREG)
2208 {
2209 try_to_add_src (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), flags | rtx_obj_flags::IN_SUBREG);
2210 iter.skip_subrtxes ();
2211 }
2212 else if (code == UNSPEC_VOLATILE)
2213 has_volatile_refs = true;
2214 else if (code == ASM_INPUT || code == ASM_OPERANDS)
2215 {
2216 has_asm = true;
2217 if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2217, __FUNCTION__); _rtx; })->volatil)
)
2218 has_volatile_refs = true;
2219 }
2220 else if (code == PRE_INC
2221 || code == PRE_DEC
2222 || code == POST_INC
2223 || code == POST_DEC
2224 || code == PRE_MODIFY
2225 || code == POST_MODIFY)
2226 {
2227 has_pre_post_modify = true;
2228
2229 unsigned int addr_flags = (base_flags
2230 | rtx_obj_flags::IS_PRE_POST_MODIFY
2231 | rtx_obj_flags::IS_READ);
2232 try_to_add_dest (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), addr_flags);
2233 if (code == PRE_MODIFY || code == POST_MODIFY)
2234 iter.substitute (XEXP (XEXP (x, 1), 1)((((((x)->u.fld[1]).rt_rtx))->u.fld[1]).rt_rtx));
2235 else
2236 iter.skip_subrtxes ();
2237 }
2238 else if (code == CALL)
2239 has_call = true;
2240 }
2241}
2242
2243/* Try to add a description of instruction pattern PAT to this object,
2244 stopping once the REF_END limit has been reached. */
2245
2246void
2247rtx_properties::try_to_add_pattern (const_rtx pat)
2248{
2249 switch (GET_CODE (pat)((enum rtx_code) (pat)->code))
2250 {
2251 case COND_EXEC:
2252 try_to_add_src (COND_EXEC_TEST (pat)(((pat)->u.fld[0]).rt_rtx));
2253 try_to_add_pattern (COND_EXEC_CODE (pat)(((pat)->u.fld[1]).rt_rtx));
2254 break;
2255
2256 case PARALLEL:
2257 {
2258 int last = XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem) - 1;
2259 for (int i = 0; i < last; ++i)
2260 try_to_add_pattern (XVECEXP (pat, 0, i)(((((pat)->u.fld[0]).rt_rtvec))->elem[i]));
2261 try_to_add_pattern (XVECEXP (pat, 0, last)(((((pat)->u.fld[0]).rt_rtvec))->elem[last]));
2262 break;
2263 }
2264
2265 case ASM_OPERANDS:
2266 for (int i = 0, len = ASM_OPERANDS_INPUT_LENGTH (pat)(((((pat)->u.fld[3]).rt_rtvec))->num_elem); i < len; ++i)
2267 try_to_add_src (ASM_OPERANDS_INPUT (pat, i)(((((pat)->u.fld[3]).rt_rtvec))->elem[i]));
2268 break;
2269
2270 case CLOBBER:
2271 try_to_add_dest (XEXP (pat, 0)(((pat)->u.fld[0]).rt_rtx), rtx_obj_flags::IS_CLOBBER);
2272 break;
2273
2274 case SET:
2275 try_to_add_dest (SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx));
2276 try_to_add_src (SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx));
2277 break;
2278
2279 default:
2280 /* All the other possibilities never store and can use a normal
2281 rtx walk. This includes:
2282
2283 - USE
2284 - TRAP_IF
2285 - PREFETCH
2286 - UNSPEC
2287 - UNSPEC_VOLATILE. */
2288 try_to_add_src (pat);
2289 break;
2290 }
2291}
2292
2293/* Try to add a description of INSN to this object, stopping once
2294 the REF_END limit has been reached. INCLUDE_NOTES is true if the
2295 description should include REG_EQUAL and REG_EQUIV notes; all such
2296 references will then be marked with rtx_obj_flags::IN_NOTE.
2297
2298 For calls, this description includes all accesses in
2299 CALL_INSN_FUNCTION_USAGE. It also include all implicit accesses
2300 to global registers by the target function. However, it does not
2301 include clobbers performed by the target function; callers that want
2302 this information should instead use the function_abi interface. */
2303
2304void
2305rtx_properties::try_to_add_insn (const rtx_insn *insn, bool include_notes)
2306{
2307 if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
2308 {
2309 /* Adding the global registers first removes a situation in which
2310 a fixed-form clobber of register R could come before a real set
2311 of register R. */
2312 if (!hard_reg_set_empty_p (global_reg_set))
2313 {
2314 unsigned int flags = (rtx_obj_flags::IS_READ
2315 | rtx_obj_flags::IS_WRITE);
2316 for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER76; ++regno)
2317 if (global_regs[regno] && ref_iter != ref_end)
2318 *ref_iter++ = rtx_obj_reference (regno, flags,
2319 reg_raw_mode(this_target_regs->x_reg_raw_mode)[regno], 0);
2320 }
2321 if (ref_iter != ref_end && !RTL_CONST_CALL_P (insn)(__extension__ ({ __typeof ((insn)) const _rtx = ((insn)); if
(((enum rtx_code) (_rtx)->code) != CALL_INSN) rtl_check_failed_flag
("RTL_CONST_CALL_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2321, __FUNCTION__); _rtx; })->unchanging)
)
2322 {
2323 auto mem_flags = rtx_obj_flags::IS_READ;
2324 if (!RTL_PURE_CALL_P (insn)(__extension__ ({ __typeof ((insn)) const _rtx = ((insn)); if
(((enum rtx_code) (_rtx)->code) != CALL_INSN) rtl_check_failed_flag
("RTL_PURE_CALL_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2324, __FUNCTION__); _rtx; })->return_val)
)
2325 mem_flags |= rtx_obj_flags::IS_WRITE;
2326 *ref_iter++ = rtx_obj_reference (MEM_REGNO, mem_flags, BLKmode((void) 0, E_BLKmode));
2327 }
2328 try_to_add_pattern (PATTERN (insn));
2329 for (rtx link = CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx); link;
2330 link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
2331 {
2332 rtx x = XEXP (link, 0)(((link)->u.fld[0]).rt_rtx);
2333 if (GET_CODE (x)((enum rtx_code) (x)->code) == CLOBBER)
2334 try_to_add_dest (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), rtx_obj_flags::IS_CLOBBER);
2335 else if (GET_CODE (x)((enum rtx_code) (x)->code) == USE)
2336 try_to_add_src (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx));
2337 }
2338 }
2339 else
2340 try_to_add_pattern (PATTERN (insn));
2341
2342 if (include_notes)
2343 for (rtx note = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); note; note = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx))
2344 if (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_EQUAL
2345 || REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)) == REG_EQUIV)
2346 try_to_add_note (XEXP (note, 0)(((note)->u.fld[0]).rt_rtx));
2347}
2348
2349/* Grow the storage by a bit while keeping the contents of the first
2350 START elements. */
2351
2352void
2353vec_rtx_properties_base::grow (ptrdiff_t start)
2354{
2355 /* The same heuristic that vec uses. */
2356 ptrdiff_t new_elems = (ref_end - ref_begin) * 3 / 2;
2357 if (ref_begin == m_storage)
2358 {
2359 ref_begin = XNEWVEC (rtx_obj_reference, new_elems)((rtx_obj_reference *) xmalloc (sizeof (rtx_obj_reference) * (
new_elems)))
;
2360 if (start)
2361 memcpy (ref_begin, m_storage, start * sizeof (rtx_obj_reference));
2362 }
2363 else
2364 ref_begin = reinterpret_cast<rtx_obj_reference *>
2365 (xrealloc (ref_begin, new_elems * sizeof (rtx_obj_reference)));
2366 ref_iter = ref_begin + start;
2367 ref_end = ref_begin + new_elems;
2368}
2369
2370/* Return nonzero if X's old contents don't survive after INSN.
2371 This will be true if X is (cc0) or if X is a register and
2372 X dies in INSN or because INSN entirely sets X.
2373
2374 "Entirely set" means set directly and not through a SUBREG, or
2375 ZERO_EXTRACT, so no trace of the old contents remains.
2376 Likewise, REG_INC does not count.
2377
2378 REG may be a hard or pseudo reg. Renumbering is not taken into account,
2379 but for this use that makes no difference, since regs don't overlap
2380 during their lifetimes. Therefore, this function may be used
2381 at any time after deaths have been computed.
2382
2383 If REG is a hard reg that occupies multiple machine registers, this
2384 function will only return 1 if each of those registers will be replaced
2385 by INSN. */
2386
2387int
2388dead_or_set_p (const rtx_insn *insn, const_rtx x)
2389{
2390 unsigned int regno, end_regno;
2391 unsigned int i;
2392
2393 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */
2394 if (GET_CODE (x)((enum rtx_code) (x)->code) == CC0)
2395 return 1;
2396
2397 gcc_assert (REG_P (x))((void)(!((((enum rtx_code) (x)->code) == REG)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2397, __FUNCTION__), 0 : 0))
;
2398
2399 regno = REGNO (x)(rhs_regno(x));
2400 end_regno = END_REGNO (x);
2401 for (i = regno; i < end_regno; i++)
2402 if (! dead_or_set_regno_p (insn, i))
2403 return 0;
2404
2405 return 1;
2406}
2407
2408/* Return TRUE iff DEST is a register or subreg of a register, is a
2409 complete rather than read-modify-write destination, and contains
2410 register TEST_REGNO. */
2411
2412static bool
2413covers_regno_no_parallel_p (const_rtx dest, unsigned int test_regno)
2414{
2415 unsigned int regno, endregno;
2416
2417 if (GET_CODE (dest)((enum rtx_code) (dest)->code) == SUBREG && !read_modify_subreg_p (dest))
2418 dest = SUBREG_REG (dest)(((dest)->u.fld[0]).rt_rtx);
2419
2420 if (!REG_P (dest)(((enum rtx_code) (dest)->code) == REG))
2421 return false;
2422
2423 regno = REGNO (dest)(rhs_regno(dest));
2424 endregno = END_REGNO (dest);
2425 return (test_regno >= regno && test_regno < endregno);
2426}
2427
2428/* Like covers_regno_no_parallel_p, but also handles PARALLELs where
2429 any member matches the covers_regno_no_parallel_p criteria. */
2430
2431static bool
2432covers_regno_p (const_rtx dest, unsigned int test_regno)
2433{
2434 if (GET_CODE (dest)((enum rtx_code) (dest)->code) == PARALLEL)
2435 {
2436 /* Some targets place small structures in registers for return
2437 values of functions, and those registers are wrapped in
2438 PARALLELs that we may see as the destination of a SET. */
2439 int i;
2440
2441 for (i = XVECLEN (dest, 0)(((((dest)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
2442 {
2443 rtx inner = XEXP (XVECEXP (dest, 0, i), 0)((((((((dest)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx)
;
2444 if (inner != NULL_RTX(rtx) 0
2445 && covers_regno_no_parallel_p (inner, test_regno))
2446 return true;
2447 }
2448
2449 return false;
2450 }
2451 else
2452 return covers_regno_no_parallel_p (dest, test_regno);
2453}
2454
2455/* Utility function for dead_or_set_p to check an individual register. */
2456
2457int
2458dead_or_set_regno_p (const rtx_insn *insn, unsigned int test_regno)
2459{
2460 const_rtx pattern;
2461
2462 /* See if there is a death note for something that includes TEST_REGNO. */
2463 if (find_regno_note (insn, REG_DEAD, test_regno))
2464 return 1;
2465
2466 if (CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN)
2467 && find_regno_fusage (insn, CLOBBER, test_regno))
2468 return 1;
2469
2470 pattern = PATTERN (insn);
2471
2472 /* If a COND_EXEC is not executed, the value survives. */
2473 if (GET_CODE (pattern)((enum rtx_code) (pattern)->code) == COND_EXEC)
2474 return 0;
2475
2476 if (GET_CODE (pattern)((enum rtx_code) (pattern)->code) == SET || GET_CODE (pattern)((enum rtx_code) (pattern)->code) == CLOBBER)
2477 return covers_regno_p (SET_DEST (pattern)(((pattern)->u.fld[0]).rt_rtx), test_regno);
2478 else if (GET_CODE (pattern)((enum rtx_code) (pattern)->code) == PARALLEL)
2479 {
2480 int i;
2481
2482 for (i = XVECLEN (pattern, 0)(((((pattern)->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
2483 {
2484 rtx body = XVECEXP (pattern, 0, i)(((((pattern)->u.fld[0]).rt_rtvec))->elem[i]);
2485
2486 if (GET_CODE (body)((enum rtx_code) (body)->code) == COND_EXEC)
2487 body = COND_EXEC_CODE (body)(((body)->u.fld[1]).rt_rtx);
2488
2489 if ((GET_CODE (body)((enum rtx_code) (body)->code) == SET || GET_CODE (body)((enum rtx_code) (body)->code) == CLOBBER)
2490 && covers_regno_p (SET_DEST (body)(((body)->u.fld[0]).rt_rtx), test_regno))
2491 return 1;
2492 }
2493 }
2494
2495 return 0;
2496}
2497
2498/* Return the reg-note of kind KIND in insn INSN, if there is one.
2499 If DATUM is nonzero, look for one whose datum is DATUM. */
2500
2501rtx
2502find_reg_note (const_rtx insn, enum reg_note kind, const_rtx datum)
2503{
2504 rtx link;
2505
2506 gcc_checking_assert (insn)((void)(!(insn) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2506, __FUNCTION__), 0 : 0))
;
2507
2508 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2509 if (! INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
)
2510 return 0;
2511 if (datum == 0)
2512 {
2513 for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
2514 if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == kind)
2515 return link;
2516 return 0;
2517 }
2518
2519 for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
2520 if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == kind && datum == XEXP (link, 0)(((link)->u.fld[0]).rt_rtx))
2521 return link;
2522 return 0;
2523}
2524
2525/* Return the reg-note of kind KIND in insn INSN which applies to register
2526 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2527 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2528 it might be the case that the note overlaps REGNO. */
2529
2530rtx
2531find_regno_note (const_rtx insn, enum reg_note kind, unsigned int regno)
2532{
2533 rtx link;
2534
2535 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2536 if (! INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
)
2537 return 0;
2538
2539 for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
2540 if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == kind
2541 /* Verify that it is a register, so that scratch and MEM won't cause a
2542 problem here. */
2543 && REG_P (XEXP (link, 0))(((enum rtx_code) ((((link)->u.fld[0]).rt_rtx))->code) ==
REG)
2544 && REGNO (XEXP (link, 0))(rhs_regno((((link)->u.fld[0]).rt_rtx))) <= regno
2545 && END_REGNO (XEXP (link, 0)(((link)->u.fld[0]).rt_rtx)) > regno)
2546 return link;
2547 return 0;
2548}
2549
2550/* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2551 has such a note. */
2552
2553rtx
2554find_reg_equal_equiv_note (const_rtx insn)
2555{
2556 rtx link;
2557
2558 if (!INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
)
2559 return 0;
2560
2561 for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
2562 if (REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == REG_EQUAL
2563 || REG_NOTE_KIND (link)((enum reg_note) ((machine_mode) (link)->mode)) == REG_EQUIV)
2564 {
2565 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2566 insns that have multiple sets. Checking single_set to
2567 make sure of this is not the proper check, as explained
2568 in the comment in set_unique_reg_note.
2569
2570 This should be changed into an assert. */
2571 if (GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == PARALLEL && multiple_sets (insn))
2572 return 0;
2573 return link;
2574 }
2575 return NULLnullptr;
2576}
2577
2578/* Check whether INSN is a single_set whose source is known to be
2579 equivalent to a constant. Return that constant if so, otherwise
2580 return null. */
2581
2582rtx
2583find_constant_src (const rtx_insn *insn)
2584{
2585 rtx note, set, x;
2586
2587 set = single_set (insn);
2588 if (set)
2589 {
2590 x = avoid_constant_pool_reference (SET_SRC (set)(((set)->u.fld[1]).rt_rtx));
2591 if (CONSTANT_P (x)((rtx_class[(int) (((enum rtx_code) (x)->code))]) == RTX_CONST_OBJ
)
)
2592 return x;
2593 }
2594
2595 note = find_reg_equal_equiv_note (insn);
2596 if (note && CONSTANT_P (XEXP (note, 0))((rtx_class[(int) (((enum rtx_code) ((((note)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
)
2597 return XEXP (note, 0)(((note)->u.fld[0]).rt_rtx);
2598
2599 return NULL_RTX(rtx) 0;
2600}
2601
2602/* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2603 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2604
2605int
2606find_reg_fusage (const_rtx insn, enum rtx_code code, const_rtx datum)
2607{
2608 /* If it's not a CALL_INSN, it can't possibly have a
2609 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2610 if (!CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN))
2611 return 0;
2612
2613 gcc_assert (datum)((void)(!(datum) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2613, __FUNCTION__), 0 : 0))
;
2614
2615 if (!REG_P (datum)(((enum rtx_code) (datum)->code) == REG))
2616 {
2617 rtx link;
2618
2619 for (link = CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx);
2620 link;
2621 link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
2622 if (GET_CODE (XEXP (link, 0))((enum rtx_code) ((((link)->u.fld[0]).rt_rtx))->code) == code
2623 && rtx_equal_p (datum, XEXP (XEXP (link, 0), 0)((((((link)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx)))
2624 return 1;
2625 }
2626 else
2627 {
2628 unsigned int regno = REGNO (datum)(rhs_regno(datum));
2629
2630 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2631 to pseudo registers, so don't bother checking. */
2632
2633 if (regno < FIRST_PSEUDO_REGISTER76)
2634 {
2635 unsigned int end_regno = END_REGNO (datum);
2636 unsigned int i;
2637
2638 for (i = regno; i < end_regno; i++)
2639 if (find_regno_fusage (insn, code, i))
2640 return 1;
2641 }
2642 }
2643
2644 return 0;
2645}
2646
2647/* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2648 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2649
2650int
2651find_regno_fusage (const_rtx insn, enum rtx_code code, unsigned int regno)
2652{
2653 rtx link;
2654
2655 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2656 to pseudo registers, so don't bother checking. */
2657
2658 if (regno >= FIRST_PSEUDO_REGISTER76
2659 || !CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN) )
2660 return 0;
2661
2662 for (link = CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
2663 {
2664 rtx op, reg;
2665
2666 if (GET_CODE (op = XEXP (link, 0))((enum rtx_code) (op = (((link)->u.fld[0]).rt_rtx))->code
)
== code
2667 && REG_P (reg = XEXP (op, 0))(((enum rtx_code) (reg = (((op)->u.fld[0]).rt_rtx))->code
) == REG)
2668 && REGNO (reg)(rhs_regno(reg)) <= regno
2669 && END_REGNO (reg) > regno)
2670 return 1;
2671 }
2672
2673 return 0;
2674}
2675
2676
2677/* Return true if KIND is an integer REG_NOTE. */
2678
2679static bool
2680int_reg_note_p (enum reg_note kind)
2681{
2682 return kind == REG_BR_PROB;
2683}
2684
2685/* Allocate a register note with kind KIND and datum DATUM. LIST is
2686 stored as the pointer to the next register note. */
2687
2688rtx
2689alloc_reg_note (enum reg_note kind, rtx datum, rtx list)
2690{
2691 rtx note;
2692
2693 gcc_checking_assert (!int_reg_note_p (kind))((void)(!(!int_reg_note_p (kind)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2693, __FUNCTION__), 0 : 0))
;
2694 switch (kind)
2695 {
2696 case REG_CC_SETTER:
2697 case REG_CC_USER:
2698 case REG_LABEL_TARGET:
2699 case REG_LABEL_OPERAND:
2700 case REG_TM:
2701 /* These types of register notes use an INSN_LIST rather than an
2702 EXPR_LIST, so that copying is done right and dumps look
2703 better. */
2704 note = alloc_INSN_LIST (datum, list);
2705 PUT_REG_NOTE_KIND (note, kind)((note)->mode = ((machine_mode) (kind)));
2706 break;
2707
2708 default:
2709 note = alloc_EXPR_LIST (kind, datum, list);
2710 break;
2711 }
2712
2713 return note;
2714}
2715
2716/* Add register note with kind KIND and datum DATUM to INSN. */
2717
2718void
2719add_reg_note (rtx insn, enum reg_note kind, rtx datum)
2720{
2721 REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) = alloc_reg_note (kind, datum, REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx));
2722}
2723
2724/* Add an integer register note with kind KIND and datum DATUM to INSN. */
2725
2726void
2727add_int_reg_note (rtx_insn *insn, enum reg_note kind, int datum)
2728{
2729 gcc_checking_assert (int_reg_note_p (kind))((void)(!(int_reg_note_p (kind)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2729, __FUNCTION__), 0 : 0))
;
2730 REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) = gen_rtx_INT_LIST ((machine_mode) kind,gen_rtx_fmt_ie_stat ((INT_LIST), (((machine_mode) kind)), ((datum
)), (((((insn)->u.fld[6]).rt_rtx))) )
2731 datum, REG_NOTES (insn))gen_rtx_fmt_ie_stat ((INT_LIST), (((machine_mode) kind)), ((datum
)), (((((insn)->u.fld[6]).rt_rtx))) )
;
2732}
2733
2734/* Add a REG_ARGS_SIZE note to INSN with value VALUE. */
2735
2736void
2737add_args_size_note (rtx_insn *insn, poly_int64 value)
2738{
2739 gcc_checking_assert (!find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX))((void)(!(!find_reg_note (insn, REG_ARGS_SIZE, (rtx) 0)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2739, __FUNCTION__), 0 : 0))
;
2740 add_reg_note (insn, REG_ARGS_SIZE, gen_int_mode (value, Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
));
2741}
2742
2743/* Add a register note like NOTE to INSN. */
2744
2745void
2746add_shallow_copy_of_reg_note (rtx_insn *insn, rtx note)
2747{
2748 if (GET_CODE (note)((enum rtx_code) (note)->code) == INT_LIST)
2749 add_int_reg_note (insn, REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)), XINT (note, 0)(((note)->u.fld[0]).rt_int));
2750 else
2751 add_reg_note (insn, REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)), XEXP (note, 0)(((note)->u.fld[0]).rt_rtx));
2752}
2753
2754/* Duplicate NOTE and return the copy. */
2755rtx
2756duplicate_reg_note (rtx note)
2757{
2758 reg_note kind = REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode));
2759
2760 if (GET_CODE (note)((enum rtx_code) (note)->code) == INT_LIST)
2761 return gen_rtx_INT_LIST ((machine_mode) kind, XINT (note, 0), NULL_RTX)gen_rtx_fmt_ie_stat ((INT_LIST), (((machine_mode) kind)), (((
((note)->u.fld[0]).rt_int))), (((rtx) 0)) )
;
2762 else if (GET_CODE (note)((enum rtx_code) (note)->code) == EXPR_LIST)
2763 return alloc_reg_note (kind, copy_insn_1 (XEXP (note, 0)(((note)->u.fld[0]).rt_rtx)), NULL_RTX(rtx) 0);
2764 else
2765 return alloc_reg_note (kind, XEXP (note, 0)(((note)->u.fld[0]).rt_rtx), NULL_RTX(rtx) 0);
2766}
2767
2768/* Remove register note NOTE from the REG_NOTES of INSN. */
2769
2770void
2771remove_note (rtx_insn *insn, const_rtx note)
2772{
2773 rtx link;
2774
2775 if (note == NULL_RTX(rtx) 0)
2776 return;
2777
2778 if (REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) == note)
2779 REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx) = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx);
2780 else
2781 for (link = REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx); link; link = XEXP (link, 1)(((link)->u.fld[1]).rt_rtx))
2782 if (XEXP (link, 1)(((link)->u.fld[1]).rt_rtx) == note)
2783 {
2784 XEXP (link, 1)(((link)->u.fld[1]).rt_rtx) = XEXP (note, 1)(((note)->u.fld[1]).rt_rtx);
2785 break;
2786 }
2787
2788 switch (REG_NOTE_KIND (note)((enum reg_note) ((machine_mode) (note)->mode)))
2789 {
2790 case REG_EQUAL:
2791 case REG_EQUIV:
2792 df_notes_rescan (insn);
2793 break;
2794 default:
2795 break;
2796 }
2797}
2798
2799/* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes.
2800 If NO_RESCAN is false and any notes were removed, call
2801 df_notes_rescan. Return true if any note has been removed. */
2802
2803bool
2804remove_reg_equal_equiv_notes (rtx_insn *insn, bool no_rescan)
2805{
2806 rtx *loc;
2807 bool ret = false;
2808
2809 loc = &REG_NOTES (insn)(((insn)->u.fld[6]).rt_rtx);
2810 while (*loc)
2811 {
2812 enum reg_note kind = REG_NOTE_KIND (*loc)((enum reg_note) ((machine_mode) (*loc)->mode));
2813 if (kind == REG_EQUAL || kind == REG_EQUIV)
2814 {
2815 *loc = XEXP (*loc, 1)(((*loc)->u.fld[1]).rt_rtx);
2816 ret = true;
2817 }
2818 else
2819 loc = &XEXP (*loc, 1)(((*loc)->u.fld[1]).rt_rtx);
2820 }
2821 if (ret && !no_rescan)
2822 df_notes_rescan (insn);
2823 return ret;
2824}
2825
2826/* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2827
2828void
2829remove_reg_equal_equiv_notes_for_regno (unsigned int regno)
2830{
2831 df_ref eq_use;
2832
2833 if (!df)
2834 return;
2835
2836 /* This loop is a little tricky. We cannot just go down the chain because
2837 it is being modified by some actions in the loop. So we just iterate
2838 over the head. We plan to drain the list anyway. */
2839 while ((eq_use = DF_REG_EQ_USE_CHAIN (regno)(df->eq_use_regs[(regno)]->reg_chain)) != NULLnullptr)
2840 {
2841 rtx_insn *insn = DF_REF_INSN (eq_use)((eq_use)->base.insn_info->insn);
2842 rtx note = find_reg_equal_equiv_note (insn);
2843
2844 /* This assert is generally triggered when someone deletes a REG_EQUAL
2845 or REG_EQUIV note by hacking the list manually rather than calling
2846 remove_note. */
2847 gcc_assert (note)((void)(!(note) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2847, __FUNCTION__), 0 : 0))
;
2848
2849 remove_note (insn, note);
2850 }
2851}
2852
2853/* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2854 return 1 if it is found. A simple equality test is used to determine if
2855 NODE matches. */
2856
2857bool
2858in_insn_list_p (const rtx_insn_list *listp, const rtx_insn *node)
2859{
2860 const_rtx x;
2861
2862 for (x = listp; x; x = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx))
2863 if (node == XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
2864 return true;
2865
2866 return false;
2867}
2868
2869/* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2870 remove that entry from the list if it is found.
2871
2872 A simple equality test is used to determine if NODE matches. */
2873
2874void
2875remove_node_from_expr_list (const_rtx node, rtx_expr_list **listp)
2876{
2877 rtx_expr_list *temp = *listp;
2878 rtx_expr_list *prev = NULLnullptr;
2879
2880 while (temp)
2881 {
2882 if (node == temp->element ())
2883 {
2884 /* Splice the node out of the list. */
2885 if (prev)
2886 XEXP (prev, 1)(((prev)->u.fld[1]).rt_rtx) = temp->next ();
2887 else
2888 *listp = temp->next ();
2889
2890 return;
2891 }
2892
2893 prev = temp;
2894 temp = temp->next ();
2895 }
2896}
2897
2898/* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2899 remove that entry from the list if it is found.
2900
2901 A simple equality test is used to determine if NODE matches. */
2902
2903void
2904remove_node_from_insn_list (const rtx_insn *node, rtx_insn_list **listp)
2905{
2906 rtx_insn_list *temp = *listp;
2907 rtx_insn_list *prev = NULLnullptr;
2908
2909 while (temp)
2910 {
2911 if (node == temp->insn ())
2912 {
2913 /* Splice the node out of the list. */
2914 if (prev)
2915 XEXP (prev, 1)(((prev)->u.fld[1]).rt_rtx) = temp->next ();
2916 else
2917 *listp = temp->next ();
2918
2919 return;
2920 }
2921
2922 prev = temp;
2923 temp = temp->next ();
2924 }
2925}
2926
2927/* Nonzero if X contains any volatile instructions. These are instructions
2928 which may cause unpredictable machine state instructions, and thus no
2929 instructions or register uses should be moved or combined across them.
2930 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2931
2932int
2933volatile_insn_p (const_rtx x)
2934{
2935 const RTX_CODEenum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
2936 switch (code)
2937 {
2938 case LABEL_REF:
2939 case SYMBOL_REF:
2940 case CONST:
2941 CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR
:
2942 case CC0:
2943 case PC:
2944 case REG:
2945 case SCRATCH:
2946 case CLOBBER:
2947 case ADDR_VEC:
2948 case ADDR_DIFF_VEC:
2949 case CALL:
2950 case MEM:
2951 return 0;
2952
2953 case UNSPEC_VOLATILE:
2954 return 1;
2955
2956 case ASM_INPUT:
2957 case ASM_OPERANDS:
2958 if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 2958, __FUNCTION__); _rtx; })->volatil)
)
2959 return 1;
2960
2961 default:
2962 break;
2963 }
2964
2965 /* Recursively scan the operands of this expression. */
2966
2967 {
2968 const char *const fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
2969 int i;
2970
2971 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
2972 {
2973 if (fmt[i] == 'e')
2974 {
2975 if (volatile_insn_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx)))
2976 return 1;
2977 }
2978 else if (fmt[i] == 'E')
2979 {
2980 int j;
2981 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
2982 if (volatile_insn_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])))
2983 return 1;
2984 }
2985 }
2986 }
2987 return 0;
2988}
2989
2990/* Nonzero if X contains any volatile memory references
2991 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2992
2993int
2994volatile_refs_p (const_rtx x)
2995{
2996 const RTX_CODEenum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
2997 switch (code)
2998 {
2999 case LABEL_REF:
3000 case SYMBOL_REF:
3001 case CONST:
3002 CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR
:
3003 case CC0:
3004 case PC:
3005 case REG:
3006 case SCRATCH:
3007 case CLOBBER:
3008 case ADDR_VEC:
3009 case ADDR_DIFF_VEC:
3010 return 0;
3011
3012 case UNSPEC_VOLATILE:
3013 return 1;
3014
3015 case MEM:
3016 case ASM_INPUT:
3017 case ASM_OPERANDS:
3018 if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3018, __FUNCTION__); _rtx; })->volatil)
)
3019 return 1;
3020
3021 default:
3022 break;
3023 }
3024
3025 /* Recursively scan the operands of this expression. */
3026
3027 {
3028 const char *const fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
3029 int i;
3030
3031 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
3032 {
3033 if (fmt[i] == 'e')
3034 {
3035 if (volatile_refs_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx)))
3036 return 1;
3037 }
3038 else if (fmt[i] == 'E')
3039 {
3040 int j;
3041 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
3042 if (volatile_refs_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])))
3043 return 1;
3044 }
3045 }
3046 }
3047 return 0;
3048}
3049
3050/* Similar to above, except that it also rejects register pre- and post-
3051 incrementing. */
3052
3053int
3054side_effects_p (const_rtx x)
3055{
3056 const RTX_CODEenum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
3057 switch (code)
3058 {
3059 case LABEL_REF:
3060 case SYMBOL_REF:
3061 case CONST:
3062 CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR
:
3063 case CC0:
3064 case PC:
3065 case REG:
3066 case SCRATCH:
3067 case ADDR_VEC:
3068 case ADDR_DIFF_VEC:
3069 case VAR_LOCATION:
3070 return 0;
3071
3072 case CLOBBER:
3073 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c
3074 when some combination can't be done. If we see one, don't think
3075 that we can simplify the expression. */
3076 return (GET_MODE (x)((machine_mode) (x)->mode) != VOIDmode((void) 0, E_VOIDmode));
3077
3078 case PRE_INC:
3079 case PRE_DEC:
3080 case POST_INC:
3081 case POST_DEC:
3082 case PRE_MODIFY:
3083 case POST_MODIFY:
3084 case CALL:
3085 case UNSPEC_VOLATILE:
3086 return 1;
3087
3088 case MEM:
3089 case ASM_INPUT:
3090 case ASM_OPERANDS:
3091 if (MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3091, __FUNCTION__); _rtx; })->volatil)
)
3092 return 1;
3093
3094 default:
3095 break;
3096 }
3097
3098 /* Recursively scan the operands of this expression. */
3099
3100 {
3101 const char *fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
3102 int i;
3103
3104 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
3105 {
3106 if (fmt[i] == 'e')
3107 {
3108 if (side_effects_p (XEXP (x, i)(((x)->u.fld[i]).rt_rtx)))
3109 return 1;
3110 }
3111 else if (fmt[i] == 'E')
3112 {
3113 int j;
3114 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
3115 if (side_effects_p (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])))
3116 return 1;
3117 }
3118 }
3119 }
3120 return 0;
3121}
3122
3123/* Return nonzero if evaluating rtx X might cause a trap.
3124 FLAGS controls how to consider MEMs. A nonzero means the context
3125 of the access may have changed from the original, such that the
3126 address may have become invalid. */
3127
3128int
3129may_trap_p_1 (const_rtx x, unsigned flags)
3130{
3131 int i;
3132 enum rtx_code code;
3133 const char *fmt;
3134
3135 /* We make no distinction currently, but this function is part of
3136 the internal target-hooks ABI so we keep the parameter as
3137 "unsigned flags". */
3138 bool code_changed = flags != 0;
3139
3140 if (x == 0)
3141 return 0;
3142 code = GET_CODE (x)((enum rtx_code) (x)->code);
3143 switch (code)
3144 {
3145 /* Handle these cases quickly. */
3146 CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR
:
3147 case SYMBOL_REF:
3148 case LABEL_REF:
3149 case CONST:
3150 case PC:
3151 case CC0:
3152 case REG:
3153 case SCRATCH:
3154 return 0;
3155
3156 case UNSPEC:
3157 return targetm.unspec_may_trap_p (x, flags);
3158
3159 case UNSPEC_VOLATILE:
3160 case ASM_INPUT:
3161 case TRAP_IF:
3162 return 1;
3163
3164 case ASM_OPERANDS:
3165 return MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3165, __FUNCTION__); _rtx; })->volatil)
;
3166
3167 /* Memory ref can trap unless it's a static var or a stack slot. */
3168 case MEM:
3169 /* Recognize specific pattern of stack checking probes. */
3170 if (flag_stack_checkglobal_options.x_flag_stack_check
3171 && MEM_VOLATILE_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM && ((enum rtx_code
) (_rtx)->code) != ASM_OPERANDS && ((enum rtx_code
) (_rtx)->code) != ASM_INPUT) rtl_check_failed_flag ("MEM_VOLATILE_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3171, __FUNCTION__); _rtx; })->volatil)
3172 && XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
3173 return 1;
3174 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
3175 reference; moving it out of context such as when moving code
3176 when optimizing, might cause its address to become invalid. */
3177 code_changed
3178 || !MEM_NOTRAP_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag ("MEM_NOTRAP_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3178, __FUNCTION__); _rtx; })->call)
)
3179 {
3180 poly_int64 size = MEM_SIZE_KNOWN_P (x)(get_mem_attrs (x)->size_known_p) ? MEM_SIZE (x)(get_mem_attrs (x)->size) : -1;
3181 return rtx_addr_can_trap_p_1 (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), 0, size,
3182 GET_MODE (x)((machine_mode) (x)->mode), code_changed);
3183 }
3184
3185 return 0;
3186
3187 /* Division by a non-constant might trap. */
3188 case DIV:
3189 case MOD:
3190 case UDIV:
3191 case UMOD:
3192 if (HONOR_SNANS (x))
3193 return 1;
3194 if (FLOAT_MODE_P (GET_MODE (x))(((enum mode_class) mode_class[((machine_mode) (x)->mode)]
) == MODE_FLOAT || ((enum mode_class) mode_class[((machine_mode
) (x)->mode)]) == MODE_DECIMAL_FLOAT || ((enum mode_class)
mode_class[((machine_mode) (x)->mode)]) == MODE_COMPLEX_FLOAT
|| ((enum mode_class) mode_class[((machine_mode) (x)->mode
)]) == MODE_VECTOR_FLOAT)
)
3195 return flag_trapping_mathglobal_options.x_flag_trapping_math;
3196 if (!CONSTANT_P (XEXP (x, 1))((rtx_class[(int) (((enum rtx_code) ((((x)->u.fld[1]).rt_rtx
))->code))]) == RTX_CONST_OBJ)
|| (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx) == const0_rtx(const_int_rtx[64])))
3197 return 1;
3198 if (GET_CODE (XEXP (x, 1))((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_VECTOR)
3199 {
3200 /* For CONST_VECTOR, return 1 if any element is or might be zero. */
3201 unsigned int n_elts;
3202 rtx op = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);
3203 if (!GET_MODE_NUNITS (GET_MODE (op)((machine_mode) (op)->mode)).is_constant (&n_elts))
3204 {
3205 if (!CONST_VECTOR_DUPLICATE_P (op)((__extension__ ({ __typeof ((op)) const _rtx = ((op)); if ((
(enum rtx_code) (_rtx)->code) != CONST_VECTOR) rtl_check_failed_flag
("CONST_VECTOR_NELTS_PER_PATTERN", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3205, __FUNCTION__); _rtx; }) ->u2.const_vector.nelts_per_pattern
) == 1)
)
3206 return 1;
3207 for (unsigned i = 0; i < (unsigned int) XVECLEN (op, 0)(((((op)->u.fld[0]).rt_rtvec))->num_elem); i++)
3208 if (CONST_VECTOR_ENCODED_ELT (op, i)(((((op)->u.fld[0]).rt_rtvec))->elem[i]) == const0_rtx(const_int_rtx[64]))
3209 return 1;
3210 }
3211 else
3212 for (unsigned i = 0; i < n_elts; i++)
3213 if (CONST_VECTOR_ELT (op, i)const_vector_elt (op, i) == const0_rtx(const_int_rtx[64]))
3214 return 1;
3215 }
3216 break;
3217
3218 case EXPR_LIST:
3219 /* An EXPR_LIST is used to represent a function call. This
3220 certainly may trap. */
3221 return 1;
3222
3223 case GE:
3224 case GT:
3225 case LE:
3226 case LT:
3227 case LTGT:
3228 case COMPARE:
3229 /* Some floating point comparisons may trap. */
3230 if (!flag_trapping_mathglobal_options.x_flag_trapping_math)
3231 break;
3232 /* ??? There is no machine independent way to check for tests that trap
3233 when COMPARE is used, though many targets do make this distinction.
3234 For instance, sparc uses CCFPE for compares which generate exceptions
3235 and CCFP for compares which do not generate exceptions. */
3236 if (HONOR_NANS (x))
3237 return 1;
3238 /* But often the compare has some CC mode, so check operand
3239 modes as well. */
3240 if (HONOR_NANS (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
3241 || HONOR_NANS (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
3242 return 1;
3243 break;
3244
3245 case EQ:
3246 case NE:
3247 if (HONOR_SNANS (x))
3248 return 1;
3249 /* Often comparison is CC mode, so check operand modes. */
3250 if (HONOR_SNANS (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx))
3251 || HONOR_SNANS (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx)))
3252 return 1;
3253 break;
3254
3255 case FIX:
3256 /* Conversion of floating point might trap. */
3257 if (flag_trapping_mathglobal_options.x_flag_trapping_math && HONOR_NANS (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx)))
3258 return 1;
3259 break;
3260
3261 case NEG:
3262 case ABS:
3263 case SUBREG:
3264 case VEC_MERGE:
3265 case VEC_SELECT:
3266 case VEC_CONCAT:
3267 case VEC_DUPLICATE:
3268 /* These operations don't trap even with floating point. */
3269 break;
3270
3271 default:
3272 /* Any floating arithmetic may trap. */
3273 if (FLOAT_MODE_P (GET_MODE (x))(((enum mode_class) mode_class[((machine_mode) (x)->mode)]
) == MODE_FLOAT || ((enum mode_class) mode_class[((machine_mode
) (x)->mode)]) == MODE_DECIMAL_FLOAT || ((enum mode_class)
mode_class[((machine_mode) (x)->mode)]) == MODE_COMPLEX_FLOAT
|| ((enum mode_class) mode_class[((machine_mode) (x)->mode
)]) == MODE_VECTOR_FLOAT)
&& flag_trapping_mathglobal_options.x_flag_trapping_math)
3274 return 1;
3275 }
3276
3277 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
3278 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
3279 {
3280 if (fmt[i] == 'e')
3281 {
3282 if (may_trap_p_1 (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), flags))
3283 return 1;
3284 }
3285 else if (fmt[i] == 'E')
3286 {
3287 int j;
3288 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
3289 if (may_trap_p_1 (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), flags))
3290 return 1;
3291 }
3292 }
3293 return 0;
3294}
3295
3296/* Return nonzero if evaluating rtx X might cause a trap. */
3297
3298int
3299may_trap_p (const_rtx x)
3300{
3301 return may_trap_p_1 (x, 0);
3302}
3303
3304/* Same as above, but additionally return nonzero if evaluating rtx X might
3305 cause a fault. We define a fault for the purpose of this function as a
3306 erroneous execution condition that cannot be encountered during the normal
3307 execution of a valid program; the typical example is an unaligned memory
3308 access on a strict alignment machine. The compiler guarantees that it
3309 doesn't generate code that will fault from a valid program, but this
3310 guarantee doesn't mean anything for individual instructions. Consider
3311 the following example:
3312
3313 struct S { int d; union { char *cp; int *ip; }; };
3314
3315 int foo(struct S *s)
3316 {
3317 if (s->d == 1)
3318 return *s->ip;
3319 else
3320 return *s->cp;
3321 }
3322
3323 on a strict alignment machine. In a valid program, foo will never be
3324 invoked on a structure for which d is equal to 1 and the underlying
3325 unique field of the union not aligned on a 4-byte boundary, but the
3326 expression *s->ip might cause a fault if considered individually.
3327
3328 At the RTL level, potentially problematic expressions will almost always
3329 verify may_trap_p; for example, the above dereference can be emitted as
3330 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
3331 However, suppose that foo is inlined in a caller that causes s->cp to
3332 point to a local character variable and guarantees that s->d is not set
3333 to 1; foo may have been effectively translated into pseudo-RTL as:
3334
3335 if ((reg:SI) == 1)
3336 (set (reg:SI) (mem:SI (%fp - 7)))
3337 else
3338 (set (reg:QI) (mem:QI (%fp - 7)))
3339
3340 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
3341 memory reference to a stack slot, but it will certainly cause a fault
3342 on a strict alignment machine. */
3343
3344int
3345may_trap_or_fault_p (const_rtx x)
3346{
3347 return may_trap_p_1 (x, 1);
3348}
3349
3350/* Replace any occurrence of FROM in X with TO. The function does
3351 not enter into CONST_DOUBLE for the replace.
3352
3353 Note that copying is not done so X must not be shared unless all copies
3354 are to be modified.
3355
3356 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
3357 those pointer-equal ones. */
3358
3359rtx
3360replace_rtx (rtx x, rtx from, rtx to, bool all_regs)
3361{
3362 int i, j;
3363 const char *fmt;
3364
3365 if (x == from)
3366 return to;
3367
3368 /* Allow this function to make replacements in EXPR_LISTs. */
3369 if (x == 0)
3370 return 0;
3371
3372 if (all_regs
3373 && REG_P (x)(((enum rtx_code) (x)->code) == REG)
3374 && REG_P (from)(((enum rtx_code) (from)->code) == REG)
3375 && REGNO (x)(rhs_regno(x)) == REGNO (from)(rhs_regno(from)))
3376 {
3377 gcc_assert (GET_MODE (x) == GET_MODE (from))((void)(!(((machine_mode) (x)->mode) == ((machine_mode) (from
)->mode)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3377, __FUNCTION__), 0 : 0))
;
3378 return to;
3379 }
3380 else if (GET_CODE (x)((enum rtx_code) (x)->code) == SUBREG)
3381 {
3382 rtx new_rtx = replace_rtx (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), from, to, all_regs);
3383
3384 if (CONST_INT_P (new_rtx)(((enum rtx_code) (new_rtx)->code) == CONST_INT))
3385 {
3386 x = simplify_subreg (GET_MODE (x)((machine_mode) (x)->mode), new_rtx,
3387 GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode),
3388 SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg));
3389 gcc_assert (x)((void)(!(x) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3389, __FUNCTION__), 0 : 0))
;
3390 }
3391 else
3392 SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx) = new_rtx;
3393
3394 return x;
3395 }
3396 else if (GET_CODE (x)((enum rtx_code) (x)->code) == ZERO_EXTEND)
3397 {
3398 rtx new_rtx = replace_rtx (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), from, to, all_regs);
3399
3400 if (CONST_INT_P (new_rtx)(((enum rtx_code) (new_rtx)->code) == CONST_INT))
3401 {
3402 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x)((machine_mode) (x)->mode),
3403 new_rtx, GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode));
3404 gcc_assert (x)((void)(!(x) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3404, __FUNCTION__), 0 : 0))
;
3405 }
3406 else
3407 XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) = new_rtx;
3408
3409 return x;
3410 }
3411
3412 fmt = GET_RTX_FORMAT (GET_CODE (x))(rtx_format[(int) (((enum rtx_code) (x)->code))]);
3413 for (i = GET_RTX_LENGTH (GET_CODE (x))(rtx_length[(int) (((enum rtx_code) (x)->code))]) - 1; i >= 0; i--)
3414 {
3415 if (fmt[i] == 'e')
3416 XEXP (x, i)(((x)->u.fld[i]).rt_rtx) = replace_rtx (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), from, to, all_regs);
3417 else if (fmt[i] == 'E')
3418 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
3419 XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]) = replace_rtx (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]),
3420 from, to, all_regs);
3421 }
3422
3423 return x;
3424}
3425
3426/* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3427 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3428
3429void
3430replace_label (rtx *loc, rtx old_label, rtx new_label, bool update_label_nuses)
3431{
3432 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3433 rtx x = *loc;
3434 if (JUMP_TABLE_DATA_P (x)(((enum rtx_code) (x)->code) == JUMP_TABLE_DATA))
3435 {
3436 x = PATTERN (x);
3437 rtvec vec = XVEC (x, GET_CODE (x) == ADDR_DIFF_VEC)(((x)->u.fld[((enum rtx_code) (x)->code) == ADDR_DIFF_VEC
]).rt_rtvec)
;
3438 int len = GET_NUM_ELEM (vec)((vec)->num_elem);
3439 for (int i = 0; i < len; ++i)
3440 {
3441 rtx ref = RTVEC_ELT (vec, i)((vec)->elem[i]);
3442 if (XEXP (ref, 0)(((ref)->u.fld[0]).rt_rtx) == old_label)
3443 {
3444 XEXP (ref, 0)(((ref)->u.fld[0]).rt_rtx) = new_label;
3445 if (update_label_nuses)
3446 {
3447 ++LABEL_NUSES (new_label)(((new_label)->u.fld[4]).rt_int);
3448 --LABEL_NUSES (old_label)(((old_label)->u.fld[4]).rt_int);
3449 }
3450 }
3451 }
3452 return;
3453 }
3454
3455 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3456 field. This is not handled by the iterator because it doesn't
3457 handle unprinted ('0') fields. */
3458 if (JUMP_P (x)(((enum rtx_code) (x)->code) == JUMP_INSN) && JUMP_LABEL (x)(((x)->u.fld[7]).rt_rtx) == old_label)
3459 JUMP_LABEL (x)(((x)->u.fld[7]).rt_rtx) = new_label;
3460
3461 subrtx_ptr_iterator::array_type array;
3462 FOR_EACH_SUBRTX_PTR (iter, array, loc, ALL)for (subrtx_ptr_iterator iter (array, loc, rtx_all_subrtx_bounds
); !iter.at_end (); iter.next ())
3463 {
3464 rtx *loc = *iter;
3465 if (rtx x = *loc)
3466 {
3467 if (GET_CODE (x)((enum rtx_code) (x)->code) == SYMBOL_REF
3468 && CONSTANT_POOL_ADDRESS_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
("CONSTANT_POOL_ADDRESS_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3468, __FUNCTION__); _rtx; })->unchanging)
)
3469 {
3470 rtx c = get_pool_constant (x);
3471 if (rtx_referenced_p (old_label, c))
3472 {
3473 /* Create a copy of constant C; replace the label inside
3474 but do not update LABEL_NUSES because uses in constant pool
3475 are not counted. */
3476 rtx new_c = copy_rtx (c);
3477 replace_label (&new_c, old_label, new_label, false);
3478
3479 /* Add the new constant NEW_C to constant pool and replace
3480 the old reference to constant by new reference. */
3481 rtx new_mem = force_const_mem (get_pool_mode (x), new_c);
3482 *loc = replace_rtx (x, x, XEXP (new_mem, 0)(((new_mem)->u.fld[0]).rt_rtx));
3483 }
3484 }
3485
3486 if ((GET_CODE (x)((enum rtx_code) (x)->code) == LABEL_REF
3487 || GET_CODE (x)((enum rtx_code) (x)->code) == INSN_LIST)
3488 && XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) == old_label)
3489 {
3490 XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) = new_label;
3491 if (update_label_nuses)
3492 {
3493 ++LABEL_NUSES (new_label)(((new_label)->u.fld[4]).rt_int);
3494 --LABEL_NUSES (old_label)(((old_label)->u.fld[4]).rt_int);
3495 }
3496 }
3497 }
3498 }
3499}
3500
3501void
3502replace_label_in_insn (rtx_insn *insn, rtx_insn *old_label,
3503 rtx_insn *new_label, bool update_label_nuses)
3504{
3505 rtx insn_as_rtx = insn;
3506 replace_label (&insn_as_rtx, old_label, new_label, update_label_nuses);
3507 gcc_checking_assert (insn_as_rtx == insn)((void)(!(insn_as_rtx == insn) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3507, __FUNCTION__), 0 : 0))
;
3508}
3509
3510/* Return true if X is referenced in BODY. */
3511
3512bool
3513rtx_referenced_p (const_rtx x, const_rtx body)
3514{
3515 subrtx_iterator::array_type array;
3516 FOR_EACH_SUBRTX (iter, array, body, ALL)for (subrtx_iterator iter (array, body, rtx_all_subrtx_bounds
); !iter.at_end (); iter.next ())
3517 if (const_rtx y = *iter)
3518 {
3519 /* Check if a label_ref Y refers to label X. */
3520 if (GET_CODE (y)((enum rtx_code) (y)->code) == LABEL_REF
3521 && LABEL_P (x)(((enum rtx_code) (x)->code) == CODE_LABEL)
3522 && label_ref_label (y) == x)
3523 return true;
3524
3525 if (rtx_equal_p (x, y))
3526 return true;
3527
3528 /* If Y is a reference to pool constant traverse the constant. */
3529 if (GET_CODE (y)((enum rtx_code) (y)->code) == SYMBOL_REF
3530 && CONSTANT_POOL_ADDRESS_P (y)(__extension__ ({ __typeof ((y)) const _rtx = ((y)); if (((enum
rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
("CONSTANT_POOL_ADDRESS_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3530, __FUNCTION__); _rtx; })->unchanging)
)
3531 iter.substitute (get_pool_constant (y));
3532 }
3533 return false;
3534}
3535
3536/* If INSN is a tablejump return true and store the label (before jump table) to
3537 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3538
3539bool
3540tablejump_p (const rtx_insn *insn, rtx_insn **labelp,
3541 rtx_jump_table_data **tablep)
3542{
3543 if (!JUMP_P (insn)(((enum rtx_code) (insn)->code) == JUMP_INSN))
3544 return false;
3545
3546 rtx target = JUMP_LABEL (insn)(((insn)->u.fld[7]).rt_rtx);
3547 if (target == NULL_RTX(rtx) 0 || ANY_RETURN_P (target)(((enum rtx_code) (target)->code) == RETURN || ((enum rtx_code
) (target)->code) == SIMPLE_RETURN)
)
3548 return false;
3549
3550 rtx_insn *label = as_a<rtx_insn *> (target);
3551 rtx_insn *table = next_insn (label);
3552 if (table == NULL_RTX(rtx) 0 || !JUMP_TABLE_DATA_P (table)(((enum rtx_code) (table)->code) == JUMP_TABLE_DATA))
3553 return false;
3554
3555 if (labelp)
3556 *labelp = label;
3557 if (tablep)
3558 *tablep = as_a <rtx_jump_table_data *> (table);
3559 return true;
3560}
3561
3562/* For INSN known to satisfy tablejump_p, determine if it actually is a
3563 CASESI. Return the insn pattern if so, NULL_RTX otherwise. */
3564
3565rtx
3566tablejump_casesi_pattern (const rtx_insn *insn)
3567{
3568 rtx tmp;
3569
3570 if ((tmp = single_set (insn)) != NULLnullptr
3571 && SET_DEST (tmp)(((tmp)->u.fld[0]).rt_rtx) == pc_rtx
3572 && GET_CODE (SET_SRC (tmp))((enum rtx_code) ((((tmp)->u.fld[1]).rt_rtx))->code) == IF_THEN_ELSE
3573 && GET_CODE (XEXP (SET_SRC (tmp), 2))((enum rtx_code) (((((((tmp)->u.fld[1]).rt_rtx))->u.fld
[2]).rt_rtx))->code)
== LABEL_REF)
3574 return tmp;
3575
3576 return NULL_RTX(rtx) 0;
3577}
3578
3579/* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or
3580 constant that is not in the constant pool and not in the condition
3581 of an IF_THEN_ELSE. */
3582
3583static int
3584computed_jump_p_1 (const_rtx x)
3585{
3586 const enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
3587 int i, j;
3588 const char *fmt;
3589
3590 switch (code)
3591 {
3592 case LABEL_REF:
3593 case PC:
3594 return 0;
3595
3596 case CONST:
3597 CASE_CONST_ANYcase CONST_INT: case CONST_WIDE_INT: case CONST_POLY_INT: case
CONST_DOUBLE: case CONST_FIXED: case CONST_VECTOR
:
3598 case SYMBOL_REF:
3599 case REG:
3600 return 1;
3601
3602 case MEM:
3603 return ! (GET_CODE (XEXP (x, 0))((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == SYMBOL_REF
3604 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))(__extension__ ({ __typeof (((((x)->u.fld[0]).rt_rtx))) const
_rtx = (((((x)->u.fld[0]).rt_rtx))); if (((enum rtx_code)
(_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag ("CONSTANT_POOL_ADDRESS_P"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3604, __FUNCTION__); _rtx; })->unchanging)
);
3605
3606 case IF_THEN_ELSE:
3607 return (computed_jump_p_1 (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx))
3608 || computed_jump_p_1 (XEXP (x, 2)(((x)->u.fld[2]).rt_rtx)));
3609
3610 default:
3611 break;
3612 }
3613
3614 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
3615 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
3616 {
3617 if (fmt[i] == 'e'
3618 && computed_jump_p_1 (XEXP (x, i)(((x)->u.fld[i]).rt_rtx)))
3619 return 1;
3620
3621 else if (fmt[i] == 'E')
3622 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
3623 if (computed_jump_p_1 (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j])))
3624 return 1;
3625 }
3626
3627 return 0;
3628}
3629
3630/* Return nonzero if INSN is an indirect jump (aka computed jump).
3631
3632 Tablejumps and casesi insns are not considered indirect jumps;
3633 we can recognize them by a (use (label_ref)). */
3634
3635int
3636computed_jump_p (const rtx_insn *insn)
3637{
3638 int i;
3639 if (JUMP_P (insn)(((enum rtx_code) (insn)->code) == JUMP_INSN))
3640 {
3641 rtx pat = PATTERN (insn);
3642
3643 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3644 if (JUMP_LABEL (insn)(((insn)->u.fld[7]).rt_rtx) != NULLnullptr)
3645 return 0;
3646
3647 if (GET_CODE (pat)((enum rtx_code) (pat)->code) == PARALLEL)
3648 {
3649 int len = XVECLEN (pat, 0)(((((pat)->u.fld[0]).rt_rtvec))->num_elem);
3650 int has_use_labelref = 0;
3651
3652 for (i = len - 1; i >= 0; i--)
3653 if (GET_CODE (XVECEXP (pat, 0, i))((enum rtx_code) ((((((pat)->u.fld[0]).rt_rtvec))->elem
[i]))->code)
== USE
3654 && (GET_CODE (XEXP (XVECEXP (pat, 0, i), 0))((enum rtx_code) (((((((((pat)->u.fld[0]).rt_rtvec))->elem
[i]))->u.fld[0]).rt_rtx))->code)
3655 == LABEL_REF))
3656 {
3657 has_use_labelref = 1;
3658 break;
3659 }
3660
3661 if (! has_use_labelref)
3662 for (i = len - 1; i >= 0; i--)
3663 if (GET_CODE (XVECEXP (pat, 0, i))((enum rtx_code) ((((((pat)->u.fld[0]).rt_rtvec))->elem
[i]))->code)
== SET
3664 && SET_DEST (XVECEXP (pat, 0, i))((((((((pat)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[0]).rt_rtx)
== pc_rtx
3665 && computed_jump_p_1 (SET_SRC (XVECEXP (pat, 0, i))((((((((pat)->u.fld[0]).rt_rtvec))->elem[i]))->u.fld
[1]).rt_rtx)
))
3666 return 1;
3667 }
3668 else if (GET_CODE (pat)((enum rtx_code) (pat)->code) == SET
3669 && SET_DEST (pat)(((pat)->u.fld[0]).rt_rtx) == pc_rtx
3670 && computed_jump_p_1 (SET_SRC (pat)(((pat)->u.fld[1]).rt_rtx)))
3671 return 1;
3672 }
3673 return 0;
3674}
3675
3676
3677
3678/* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3679 the equivalent add insn and pass the result to FN, using DATA as the
3680 final argument. */
3681
3682static int
3683for_each_inc_dec_find_inc_dec (rtx mem, for_each_inc_dec_fn fn, void *data)
3684{
3685 rtx x = XEXP (mem, 0)(((mem)->u.fld[0]).rt_rtx);
3686 switch (GET_CODE (x)((enum rtx_code) (x)->code))
3687 {
3688 case PRE_INC:
3689 case POST_INC:
3690 {
3691 poly_int64 size = GET_MODE_SIZE (GET_MODE (mem)((machine_mode) (mem)->mode));
3692 rtx r1 = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
3693 rtx c = gen_int_mode (size, GET_MODE (r1)((machine_mode) (r1)->mode));
3694 return fn (mem, x, r1, r1, c, data);
3695 }
3696
3697 case PRE_DEC:
3698 case POST_DEC:
3699 {
3700 poly_int64 size = GET_MODE_SIZE (GET_MODE (mem)((machine_mode) (mem)->mode));
3701 rtx r1 = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
3702 rtx c = gen_int_mode (-size, GET_MODE (r1)((machine_mode) (r1)->mode));
3703 return fn (mem, x, r1, r1, c, data);
3704 }
3705
3706 case PRE_MODIFY:
3707 case POST_MODIFY:
3708 {
3709 rtx r1 = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
3710 rtx add = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);
3711 return fn (mem, x, r1, add, NULLnullptr, data);
3712 }
3713
3714 default:
3715 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3715, __FUNCTION__))
;
3716 }
3717}
3718
3719/* Traverse *LOC looking for MEMs that have autoinc addresses.
3720 For each such autoinc operation found, call FN, passing it
3721 the innermost enclosing MEM, the operation itself, the RTX modified
3722 by the operation, two RTXs (the second may be NULL) that, once
3723 added, represent the value to be held by the modified RTX
3724 afterwards, and DATA. FN is to return 0 to continue the
3725 traversal or any other value to have it returned to the caller of
3726 for_each_inc_dec. */
3727
3728int
3729for_each_inc_dec (rtx x,
3730 for_each_inc_dec_fn fn,
3731 void *data)
3732{
3733 subrtx_var_iterator::array_type array;
3734 FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST)for (subrtx_var_iterator iter (array, x, rtx_nonconst_subrtx_bounds
); !iter.at_end (); iter.next ())
3735 {
3736 rtx mem = *iter;
3737 if (mem
3738 && MEM_P (mem)(((enum rtx_code) (mem)->code) == MEM)
3739 && GET_RTX_CLASS (GET_CODE (XEXP (mem, 0)))(rtx_class[(int) (((enum rtx_code) ((((mem)->u.fld[0]).rt_rtx
))->code))])
== RTX_AUTOINC)
3740 {
3741 int res = for_each_inc_dec_find_inc_dec (mem, fn, data);
3742 if (res != 0)
3743 return res;
3744 iter.skip_subrtxes ();
3745 }
3746 }
3747 return 0;
3748}
3749
3750
3751/* Searches X for any reference to REGNO, returning the rtx of the
3752 reference found if any. Otherwise, returns NULL_RTX. */
3753
3754rtx
3755regno_use_in (unsigned int regno, rtx x)
3756{
3757 const char *fmt;
3758 int i, j;
3759 rtx tem;
3760
3761 if (REG_P (x)(((enum rtx_code) (x)->code) == REG) && REGNO (x)(rhs_regno(x)) == regno)
3762 return x;
3763
3764 fmt = GET_RTX_FORMAT (GET_CODE (x))(rtx_format[(int) (((enum rtx_code) (x)->code))]);
3765 for (i = GET_RTX_LENGTH (GET_CODE (x))(rtx_length[(int) (((enum rtx_code) (x)->code))]) - 1; i >= 0; i--)
3766 {
3767 if (fmt[i] == 'e')
3768 {
3769 if ((tem = regno_use_in (regno, XEXP (x, i)(((x)->u.fld[i]).rt_rtx))))
3770 return tem;
3771 }
3772 else if (fmt[i] == 'E')
3773 for (j = XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
3774 if ((tem = regno_use_in (regno , XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]))))
3775 return tem;
3776 }
3777
3778 return NULL_RTX(rtx) 0;
3779}
3780
3781/* Return a value indicating whether OP, an operand of a commutative
3782 operation, is preferred as the first or second operand. The more
3783 positive the value, the stronger the preference for being the first
3784 operand. */
3785
3786int
3787commutative_operand_precedence (rtx op)
3788{
3789 enum rtx_code code = GET_CODE (op)((enum rtx_code) (op)->code);
3790
3791 /* Constants always become the second operand. Prefer "nice" constants. */
3792 if (code == CONST_INT)
3793 return -10;
3794 if (code == CONST_WIDE_INT)
3795 return -9;
3796 if (code == CONST_POLY_INT)
3797 return -8;
3798 if (code == CONST_DOUBLE)
3799 return -8;
3800 if (code == CONST_FIXED)
3801 return -8;
3802 op = avoid_constant_pool_reference (op);
3803 code = GET_CODE (op)((enum rtx_code) (op)->code);
3804
3805 switch (GET_RTX_CLASS (code)(rtx_class[(int) (code)]))
3806 {
3807 case RTX_CONST_OBJ:
3808 if (code == CONST_INT)
3809 return -7;
3810 if (code == CONST_WIDE_INT)
3811 return -6;
3812 if (code == CONST_POLY_INT)
3813 return -5;
3814 if (code == CONST_DOUBLE)
3815 return -5;
3816 if (code == CONST_FIXED)
3817 return -5;
3818 return -4;
3819
3820 case RTX_EXTRA:
3821 /* SUBREGs of objects should come second. */
3822 if (code == SUBREG && OBJECT_P (SUBREG_REG (op))(((rtx_class[(int) (((enum rtx_code) ((((op)->u.fld[0]).rt_rtx
))->code))]) & (~1)) == (RTX_OBJ & (~1)))
)
3823 return -3;
3824 return 0;
3825
3826 case RTX_OBJ:
3827 /* Complex expressions should be the first, so decrease priority
3828 of objects. Prefer pointer objects over non pointer objects. */
3829 if ((REG_P (op)(((enum rtx_code) (op)->code) == REG) && REG_POINTER (op)(__extension__ ({ __typeof ((op)) const _rtx = ((op)); if (((
enum rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag
("REG_POINTER", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3829, __FUNCTION__); _rtx; })->frame_related)
)
3830 || (MEM_P (op)(((enum rtx_code) (op)->code) == MEM) && MEM_POINTER (op)(__extension__ ({ __typeof ((op)) const _rtx = ((op)); if (((
enum rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag
("MEM_POINTER", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3830, __FUNCTION__); _rtx; })->frame_related)
))
3831 return -1;
3832 return -2;
3833
3834 case RTX_COMM_ARITH:
3835 /* Prefer operands that are themselves commutative to be first.
3836 This helps to make things linear. In particular,
3837 (and (and (reg) (reg)) (not (reg))) is canonical. */
3838 return 4;
3839
3840 case RTX_BIN_ARITH:
3841 /* If only one operand is a binary expression, it will be the first
3842 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3843 is canonical, although it will usually be further simplified. */
3844 return 2;
3845
3846 case RTX_UNARY:
3847 /* Then prefer NEG and NOT. */
3848 if (code == NEG || code == NOT)
3849 return 1;
3850 /* FALLTHRU */
3851
3852 default:
3853 return 0;
3854 }
3855}
3856
3857/* Return 1 iff it is necessary to swap operands of commutative operation
3858 in order to canonicalize expression. */
3859
3860bool
3861swap_commutative_operands_p (rtx x, rtx y)
3862{
3863 return (commutative_operand_precedence (x)
3864 < commutative_operand_precedence (y));
3865}
3866
3867/* Return 1 if X is an autoincrement side effect and the register is
3868 not the stack pointer. */
3869int
3870auto_inc_p (const_rtx x)
3871{
3872 switch (GET_CODE (x)((enum rtx_code) (x)->code))
3873 {
3874 case PRE_INC:
3875 case POST_INC:
3876 case PRE_DEC:
3877 case POST_DEC:
3878 case PRE_MODIFY:
3879 case POST_MODIFY:
3880 /* There are no REG_INC notes for SP. */
3881 if (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx) != stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
3882 return 1;
3883 default:
3884 break;
3885 }
3886 return 0;
3887}
3888
3889/* Return nonzero if IN contains a piece of rtl that has the address LOC. */
3890int
3891loc_mentioned_in_p (rtx *loc, const_rtx in)
3892{
3893 enum rtx_code code;
3894 const char *fmt;
3895 int i, j;
3896
3897 if (!in)
3898 return 0;
3899
3900 code = GET_CODE (in)((enum rtx_code) (in)->code);
3901 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
3902 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
3903 {
3904 if (fmt[i] == 'e')
3905 {
3906 if (loc == &XEXP (in, i)(((in)->u.fld[i]).rt_rtx) || loc_mentioned_in_p (loc, XEXP (in, i)(((in)->u.fld[i]).rt_rtx)))
3907 return 1;
3908 }
3909 else if (fmt[i] == 'E')
3910 for (j = XVECLEN (in, i)(((((in)->u.fld[i]).rt_rtvec))->num_elem) - 1; j >= 0; j--)
3911 if (loc == &XVECEXP (in, i, j)(((((in)->u.fld[i]).rt_rtvec))->elem[j])
3912 || loc_mentioned_in_p (loc, XVECEXP (in, i, j)(((((in)->u.fld[i]).rt_rtvec))->elem[j])))
3913 return 1;
3914 }
3915 return 0;
3916}
3917
3918/* Reinterpret a subreg as a bit extraction from an integer and return
3919 the position of the least significant bit of the extracted value.
3920 In other words, if the extraction were performed as a shift right
3921 and mask, return the number of bits to shift right.
3922
3923 The outer value of the subreg has OUTER_BYTES bytes and starts at
3924 byte offset SUBREG_BYTE within an inner value of INNER_BYTES bytes. */
3925
3926poly_uint64
3927subreg_size_lsb (poly_uint64 outer_bytes,
3928 poly_uint64 inner_bytes,
3929 poly_uint64 subreg_byte)
3930{
3931 poly_uint64 subreg_end, trailing_bytes, byte_pos;
3932
3933 /* A paradoxical subreg begins at bit position 0. */
3934 gcc_checking_assert (ordered_p (outer_bytes, inner_bytes))((void)(!(ordered_p (outer_bytes, inner_bytes)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3934, __FUNCTION__), 0 : 0))
;
3935 if (maybe_gt (outer_bytes, inner_bytes)maybe_lt (inner_bytes, outer_bytes))
3936 {
3937 gcc_checking_assert (known_eq (subreg_byte, 0U))((void)(!((!maybe_ne (subreg_byte, 0U))) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3937, __FUNCTION__), 0 : 0))
;
3938 return 0;
3939 }
3940
3941 subreg_end = subreg_byte + outer_bytes;
3942 trailing_bytes = inner_bytes - subreg_end;
3943 if (WORDS_BIG_ENDIAN0 && BYTES_BIG_ENDIAN0)
3944 byte_pos = trailing_bytes;
3945 else if (!WORDS_BIG_ENDIAN0 && !BYTES_BIG_ENDIAN0)
3946 byte_pos = subreg_byte;
3947 else
3948 {
3949 /* When bytes and words have opposite endianness, we must be able
3950 to split offsets into words and bytes at compile time. */
3951 poly_uint64 leading_word_part
3952 = force_align_down (subreg_byte, UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
0) ? 8 : 4)
);
3953 poly_uint64 trailing_word_part
3954 = force_align_down (trailing_bytes, UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
0) ? 8 : 4)
);
3955 /* If the subreg crosses a word boundary ensure that
3956 it also begins and ends on a word boundary. */
3957 gcc_assert (known_le (subreg_end - leading_word_part,((void)(!((!maybe_lt ((unsigned int) (((global_options.x_ix86_isa_flags
& (1UL << 1)) != 0) ? 8 : 4), subreg_end - leading_word_part
)) || ((!maybe_ne (leading_word_part, subreg_byte)) &&
(!maybe_ne (trailing_word_part, trailing_bytes)))) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3960, __FUNCTION__), 0 : 0))
3958 (unsigned int) UNITS_PER_WORD)((void)(!((!maybe_lt ((unsigned int) (((global_options.x_ix86_isa_flags
& (1UL << 1)) != 0) ? 8 : 4), subreg_end - leading_word_part
)) || ((!maybe_ne (leading_word_part, subreg_byte)) &&
(!maybe_ne (trailing_word_part, trailing_bytes)))) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3960, __FUNCTION__), 0 : 0))
3959 || (known_eq (leading_word_part, subreg_byte)((void)(!((!maybe_lt ((unsigned int) (((global_options.x_ix86_isa_flags
& (1UL << 1)) != 0) ? 8 : 4), subreg_end - leading_word_part
)) || ((!maybe_ne (leading_word_part, subreg_byte)) &&
(!maybe_ne (trailing_word_part, trailing_bytes)))) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3960, __FUNCTION__), 0 : 0))
3960 && known_eq (trailing_word_part, trailing_bytes)))((void)(!((!maybe_lt ((unsigned int) (((global_options.x_ix86_isa_flags
& (1UL << 1)) != 0) ? 8 : 4), subreg_end - leading_word_part
)) || ((!maybe_ne (leading_word_part, subreg_byte)) &&
(!maybe_ne (trailing_word_part, trailing_bytes)))) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3960, __FUNCTION__), 0 : 0))
;
3961 if (WORDS_BIG_ENDIAN0)
3962 byte_pos = trailing_word_part + (subreg_byte - leading_word_part);
3963 else
3964 byte_pos = leading_word_part + (trailing_bytes - trailing_word_part);
3965 }
3966
3967 return byte_pos * BITS_PER_UNIT(8);
3968}
3969
3970/* Given a subreg X, return the bit offset where the subreg begins
3971 (counting from the least significant bit of the reg). */
3972
3973poly_uint64
3974subreg_lsb (const_rtx x)
3975{
3976 return subreg_lsb_1 (GET_MODE (x)((machine_mode) (x)->mode), GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode),
3977 SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg));
3978}
3979
3980/* Return the subreg byte offset for a subreg whose outer value has
3981 OUTER_BYTES bytes, whose inner value has INNER_BYTES bytes, and where
3982 there are LSB_SHIFT *bits* between the lsb of the outer value and the
3983 lsb of the inner value. This is the inverse of the calculation
3984 performed by subreg_lsb_1 (which converts byte offsets to bit shifts). */
3985
3986poly_uint64
3987subreg_size_offset_from_lsb (poly_uint64 outer_bytes, poly_uint64 inner_bytes,
3988 poly_uint64 lsb_shift)
3989{
3990 /* A paradoxical subreg begins at bit position 0. */
3991 gcc_checking_assert (ordered_p (outer_bytes, inner_bytes))((void)(!(ordered_p (outer_bytes, inner_bytes)) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3991, __FUNCTION__), 0 : 0))
;
3992 if (maybe_gt (outer_bytes, inner_bytes)maybe_lt (inner_bytes, outer_bytes))
3993 {
3994 gcc_checking_assert (known_eq (lsb_shift, 0U))((void)(!((!maybe_ne (lsb_shift, 0U))) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 3994, __FUNCTION__), 0 : 0))
;
3995 return 0;
3996 }
3997
3998 poly_uint64 lower_bytes = exact_div (lsb_shift, BITS_PER_UNIT(8));
3999 poly_uint64 upper_bytes = inner_bytes - (lower_bytes + outer_bytes);
4000 if (WORDS_BIG_ENDIAN0 && BYTES_BIG_ENDIAN0)
4001 return upper_bytes;
4002 else if (!WORDS_BIG_ENDIAN0 && !BYTES_BIG_ENDIAN0)
4003 return lower_bytes;
4004 else
4005 {
4006 /* When bytes and words have opposite endianness, we must be able
4007 to split offsets into words and bytes at compile time. */
4008 poly_uint64 lower_word_part = force_align_down (lower_bytes,
4009 UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
0) ? 8 : 4)
);
4010 poly_uint64 upper_word_part = force_align_down (upper_bytes,
4011 UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
0) ? 8 : 4)
);
4012 if (WORDS_BIG_ENDIAN0)
4013 return upper_word_part + (lower_bytes - lower_word_part);
4014 else
4015 return lower_word_part + (upper_bytes - upper_word_part);
4016 }
4017}
4018
4019/* Fill in information about a subreg of a hard register.
4020 xregno - A regno of an inner hard subreg_reg (or what will become one).
4021 xmode - The mode of xregno.
4022 offset - The byte offset.
4023 ymode - The mode of a top level SUBREG (or what may become one).
4024 info - Pointer to structure to fill in.
4025
4026 Rather than considering one particular inner register (and thus one
4027 particular "outer" register) in isolation, this function really uses
4028 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
4029 function does not check whether adding INFO->offset to XREGNO gives
4030 a valid hard register; even if INFO->offset + XREGNO is out of range,
4031 there might be another register of the same type that is in range.
4032 Likewise it doesn't check whether targetm.hard_regno_mode_ok accepts
4033 the new register, since that can depend on things like whether the final
4034 register number is even or odd. Callers that want to check whether
4035 this particular subreg can be replaced by a simple (reg ...) should
4036 use simplify_subreg_regno. */
4037
4038void
4039subreg_get_info (unsigned int xregno, machine_mode xmode,
4040 poly_uint64 offset, machine_mode ymode,
4041 struct subreg_info *info)
4042{
4043 unsigned int nregs_xmode, nregs_ymode;
4044
4045 gcc_assert (xregno < FIRST_PSEUDO_REGISTER)((void)(!(xregno < 76) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4045, __FUNCTION__), 0 : 0))
;
4046
4047 poly_uint64 xsize = GET_MODE_SIZE (xmode);
4048 poly_uint64 ysize = GET_MODE_SIZE (ymode);
4049
4050 bool rknown = false;
4051
4052 /* If the register representation of a non-scalar mode has holes in it,
4053 we expect the scalar units to be concatenated together, with the holes
4054 distributed evenly among the scalar units. Each scalar unit must occupy
4055 at least one register. */
4056 if (HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode)(((global_options.x_target_flags & (1U << 0)) != 0)
&& !((global_options.x_ix86_isa_flags & (1UL <<
1)) != 0) && ((((unsigned long) ((xregno)) - (unsigned
long) (0) <= (unsigned long) (7) - (unsigned long) (0))) ||
((unsigned long) ((xregno)) - (unsigned long) (36) <= (unsigned
long) (43) - (unsigned long) (36))) && ((xmode) == (
scalar_float_mode ((scalar_float_mode::from_int) E_XFmode)) ||
(xmode) == (complex_mode ((complex_mode::from_int) E_XCmode)
)))
)
4057 {
4058 /* As a consequence, we must be dealing with a constant number of
4059 scalars, and thus a constant offset and number of units. */
4060 HOST_WIDE_INTlong coffset = offset.to_constant ();
4061 HOST_WIDE_INTlong cysize = ysize.to_constant ();
4062 nregs_xmode = HARD_REGNO_NREGS_WITH_PADDING (xregno, xmode)((xmode) == (scalar_float_mode ((scalar_float_mode::from_int)
E_XFmode)) ? 4 : 8)
;
4063 unsigned int nunits = GET_MODE_NUNITS (xmode).to_constant ();
4064 scalar_mode xmode_unit = GET_MODE_INNER (xmode)(mode_to_inner (xmode));
4065 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode_unit))((void)(!((((global_options.x_target_flags & (1U <<
0)) != 0) && !((global_options.x_ix86_isa_flags &
(1UL << 1)) != 0) && ((((unsigned long) ((xregno
)) - (unsigned long) (0) <= (unsigned long) (7) - (unsigned
long) (0))) || ((unsigned long) ((xregno)) - (unsigned long)
(36) <= (unsigned long) (43) - (unsigned long) (36))) &&
((xmode_unit) == (scalar_float_mode ((scalar_float_mode::from_int
) E_XFmode)) || (xmode_unit) == (complex_mode ((complex_mode::
from_int) E_XCmode))))) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4065, __FUNCTION__), 0 : 0))
;
4066 gcc_assert (nregs_xmode((void)(!(nregs_xmode == (nunits * ((xmode_unit) == (scalar_float_mode
((scalar_float_mode::from_int) E_XFmode)) ? 4 : 8))) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4068, __FUNCTION__), 0 : 0))
4067 == (nunits((void)(!(nregs_xmode == (nunits * ((xmode_unit) == (scalar_float_mode
((scalar_float_mode::from_int) E_XFmode)) ? 4 : 8))) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4068, __FUNCTION__), 0 : 0))
4068 * HARD_REGNO_NREGS_WITH_PADDING (xregno, xmode_unit)))((void)(!(nregs_xmode == (nunits * ((xmode_unit) == (scalar_float_mode
((scalar_float_mode::from_int) E_XFmode)) ? 4 : 8))) ? fancy_abort
("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4068, __FUNCTION__), 0 : 0))
;
4069 gcc_assert (hard_regno_nregs (xregno, xmode)((void)(!(hard_regno_nregs (xregno, xmode) == hard_regno_nregs
(xregno, xmode_unit) * nunits) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4070, __FUNCTION__), 0 : 0))
4070 == hard_regno_nregs (xregno, xmode_unit) * nunits)((void)(!(hard_regno_nregs (xregno, xmode) == hard_regno_nregs
(xregno, xmode_unit) * nunits) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4070, __FUNCTION__), 0 : 0))
;
4071
4072 /* You can only ask for a SUBREG of a value with holes in the middle
4073 if you don't cross the holes. (Such a SUBREG should be done by
4074 picking a different register class, or doing it in memory if
4075 necessary.) An example of a value with holes is XCmode on 32-bit
4076 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
4077 3 for each part, but in memory it's two 128-bit parts.
4078 Padding is assumed to be at the end (not necessarily the 'high part')
4079 of each unit. */
4080 if ((coffset / GET_MODE_SIZE (xmode_unit) + 1 < nunits)
4081 && (coffset / GET_MODE_SIZE (xmode_unit)
4082 != ((coffset + cysize - 1) / GET_MODE_SIZE (xmode_unit))))
4083 {
4084 info->representable_p = false;
4085 rknown = true;
4086 }
4087 }
4088 else
4089 nregs_xmode = hard_regno_nregs (xregno, xmode);
4090
4091 nregs_ymode = hard_regno_nregs (xregno, ymode);
4092
4093 /* Subreg sizes must be ordered, so that we can tell whether they are
4094 partial, paradoxical or complete. */
4095 gcc_checking_assert (ordered_p (xsize, ysize))((void)(!(ordered_p (xsize, ysize)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4095, __FUNCTION__), 0 : 0))
;
4096
4097 /* Paradoxical subregs are otherwise valid. */
4098 if (!rknown && known_eq (offset, 0U)(!maybe_ne (offset, 0U)) && maybe_gt (ysize, xsize)maybe_lt (xsize, ysize))
4099 {
4100 info->representable_p = true;
4101 /* If this is a big endian paradoxical subreg, which uses more
4102 actual hard registers than the original register, we must
4103 return a negative offset so that we find the proper highpart
4104 of the register.
4105
4106 We assume that the ordering of registers within a multi-register
4107 value has a consistent endianness: if bytes and register words
4108 have different endianness, the hard registers that make up a
4109 multi-register value must be at least word-sized. */
4110 if (REG_WORDS_BIG_ENDIAN0)
4111 info->offset = (int) nregs_xmode - (int) nregs_ymode;
4112 else
4113 info->offset = 0;
4114 info->nregs = nregs_ymode;
4115 return;
4116 }
4117
4118 /* If registers store different numbers of bits in the different
4119 modes, we cannot generally form this subreg. */
4120 poly_uint64 regsize_xmode, regsize_ymode;
4121 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode)(((global_options.x_target_flags & (1U << 0)) != 0)
&& !((global_options.x_ix86_isa_flags & (1UL <<
1)) != 0) && ((((unsigned long) ((xregno)) - (unsigned
long) (0) <= (unsigned long) (7) - (unsigned long) (0))) ||
((unsigned long) ((xregno)) - (unsigned long) (36) <= (unsigned
long) (43) - (unsigned long) (36))) && ((xmode) == (
scalar_float_mode ((scalar_float_mode::from_int) E_XFmode)) ||
(xmode) == (complex_mode ((complex_mode::from_int) E_XCmode)
)))
4122 && !HARD_REGNO_NREGS_HAS_PADDING (xregno, ymode)(((global_options.x_target_flags & (1U << 0)) != 0)
&& !((global_options.x_ix86_isa_flags & (1UL <<
1)) != 0) && ((((unsigned long) ((xregno)) - (unsigned
long) (0) <= (unsigned long) (7) - (unsigned long) (0))) ||
((unsigned long) ((xregno)) - (unsigned long) (36) <= (unsigned
long) (43) - (unsigned long) (36))) && ((ymode) == (
scalar_float_mode ((scalar_float_mode::from_int) E_XFmode)) ||
(ymode) == (complex_mode ((complex_mode::from_int) E_XCmode)
)))
4123 && multiple_p (xsize, nregs_xmode, &regsize_xmode)
4124 && multiple_p (ysize, nregs_ymode, &regsize_ymode))
4125 {
4126 if (!rknown
4127 && ((nregs_ymode > 1 && maybe_gt (regsize_xmode, regsize_ymode)maybe_lt (regsize_ymode, regsize_xmode))
4128 || (nregs_xmode > 1 && maybe_gt (regsize_ymode, regsize_xmode)maybe_lt (regsize_xmode, regsize_ymode))))
4129 {
4130 info->representable_p = false;
4131 if (!can_div_away_from_zero_p (ysize, regsize_xmode, &info->nregs)
4132 || !can_div_trunc_p (offset, regsize_xmode, &info->offset))
4133 /* Checked by validate_subreg. We must know at compile time
4134 which inner registers are being accessed. */
4135 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4135, __FUNCTION__))
;
4136 return;
4137 }
4138 /* It's not valid to extract a subreg of mode YMODE at OFFSET that
4139 would go outside of XMODE. */
4140 if (!rknown && maybe_gt (ysize + offset, xsize)maybe_lt (xsize, ysize + offset))
4141 {
4142 info->representable_p = false;
4143 info->nregs = nregs_ymode;
4144 if (!can_div_trunc_p (offset, regsize_xmode, &info->offset))
4145 /* Checked by validate_subreg. We must know at compile time
4146 which inner registers are being accessed. */
4147 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4147, __FUNCTION__))
;
4148 return;
4149 }
4150 /* Quick exit for the simple and common case of extracting whole
4151 subregisters from a multiregister value. */
4152 /* ??? It would be better to integrate this into the code below,
4153 if we can generalize the concept enough and figure out how
4154 odd-sized modes can coexist with the other weird cases we support. */
4155 HOST_WIDE_INTlong count;
4156 if (!rknown
4157 && WORDS_BIG_ENDIAN0 == REG_WORDS_BIG_ENDIAN0
4158 && known_eq (regsize_xmode, regsize_ymode)(!maybe_ne (regsize_xmode, regsize_ymode))
4159 && constant_multiple_p (offset, regsize_ymode, &count))
4160 {
4161 info->representable_p = true;
4162 info->nregs = nregs_ymode;
4163 info->offset = count;
4164 gcc_assert (info->offset + info->nregs <= (int) nregs_xmode)((void)(!(info->offset + info->nregs <= (int) nregs_xmode
) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4164, __FUNCTION__), 0 : 0))
;
4165 return;
4166 }
4167 }
4168
4169 /* Lowpart subregs are otherwise valid. */
4170 if (!rknown && known_eq (offset, subreg_lowpart_offset (ymode, xmode))(!maybe_ne (offset, subreg_lowpart_offset (ymode, xmode))))
4171 {
4172 info->representable_p = true;
4173 rknown = true;
4174
4175 if (known_eq (offset, 0U)(!maybe_ne (offset, 0U)) || nregs_xmode == nregs_ymode)
4176 {
4177 info->offset = 0;
4178 info->nregs = nregs_ymode;
4179 return;
4180 }
4181 }
4182
4183 /* Set NUM_BLOCKS to the number of independently-representable YMODE
4184 values there are in (reg:XMODE XREGNO). We can view the register
4185 as consisting of this number of independent "blocks", where each
4186 block occupies NREGS_YMODE registers and contains exactly one
4187 representable YMODE value. */
4188 gcc_assert ((nregs_xmode % nregs_ymode) == 0)((void)(!((nregs_xmode % nregs_ymode) == 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4188, __FUNCTION__), 0 : 0))
;
4189 unsigned int num_blocks = nregs_xmode / nregs_ymode;
4190
4191 /* Calculate the number of bytes in each block. This must always
4192 be exact, otherwise we don't know how to verify the constraint.
4193 These conditions may be relaxed but subreg_regno_offset would
4194 need to be redesigned. */
4195 poly_uint64 bytes_per_block = exact_div (xsize, num_blocks);
4196
4197 /* Get the number of the first block that contains the subreg and the byte
4198 offset of the subreg from the start of that block. */
4199 unsigned int block_number;
4200 poly_uint64 subblock_offset;
4201 if (!can_div_trunc_p (offset, bytes_per_block, &block_number,
4202 &subblock_offset))
4203 /* Checked by validate_subreg. We must know at compile time which
4204 inner registers are being accessed. */
4205 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4205, __FUNCTION__))
;
4206
4207 if (!rknown)
4208 {
4209 /* Only the lowpart of each block is representable. */
4210 info->representable_p
4211 = known_eq (subblock_offset,(!maybe_ne (subblock_offset, subreg_size_lowpart_offset (ysize
, bytes_per_block)))
4212 subreg_size_lowpart_offset (ysize, bytes_per_block))(!maybe_ne (subblock_offset, subreg_size_lowpart_offset (ysize
, bytes_per_block)))
;
4213 rknown = true;
4214 }
4215
4216 /* We assume that the ordering of registers within a multi-register
4217 value has a consistent endianness: if bytes and register words
4218 have different endianness, the hard registers that make up a
4219 multi-register value must be at least word-sized. */
4220 if (WORDS_BIG_ENDIAN0 != REG_WORDS_BIG_ENDIAN0)
4221 /* The block number we calculated above followed memory endianness.
4222 Convert it to register endianness by counting back from the end.
4223 (Note that, because of the assumption above, each block must be
4224 at least word-sized.) */
4225 info->offset = (num_blocks - block_number - 1) * nregs_ymode;
4226 else
4227 info->offset = block_number * nregs_ymode;
4228 info->nregs = nregs_ymode;
4229}
4230
4231/* This function returns the regno offset of a subreg expression.
4232 xregno - A regno of an inner hard subreg_reg (or what will become one).
4233 xmode - The mode of xregno.
4234 offset - The byte offset.
4235 ymode - The mode of a top level SUBREG (or what may become one).
4236 RETURN - The regno offset which would be used. */
4237unsigned int
4238subreg_regno_offset (unsigned int xregno, machine_mode xmode,
4239 poly_uint64 offset, machine_mode ymode)
4240{
4241 struct subreg_info info;
4242 subreg_get_info (xregno, xmode, offset, ymode, &info);
4243 return info.offset;
4244}
4245
4246/* This function returns true when the offset is representable via
4247 subreg_offset in the given regno.
4248 xregno - A regno of an inner hard subreg_reg (or what will become one).
4249 xmode - The mode of xregno.
4250 offset - The byte offset.
4251 ymode - The mode of a top level SUBREG (or what may become one).
4252 RETURN - Whether the offset is representable. */
4253bool
4254subreg_offset_representable_p (unsigned int xregno, machine_mode xmode,
4255 poly_uint64 offset, machine_mode ymode)
4256{
4257 struct subreg_info info;
4258 subreg_get_info (xregno, xmode, offset, ymode, &info);
4259 return info.representable_p;
4260}
4261
4262/* Return the number of a YMODE register to which
4263
4264 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
4265
4266 can be simplified. Return -1 if the subreg can't be simplified.
4267
4268 XREGNO is a hard register number. */
4269
4270int
4271simplify_subreg_regno (unsigned int xregno, machine_mode xmode,
4272 poly_uint64 offset, machine_mode ymode)
4273{
4274 struct subreg_info info;
4275 unsigned int yregno;
4276
4277 /* Give the backend a chance to disallow the mode change. */
4278 if (GET_MODE_CLASS (xmode)((enum mode_class) mode_class[xmode]) != MODE_COMPLEX_INT
4279 && GET_MODE_CLASS (xmode)((enum mode_class) mode_class[xmode]) != MODE_COMPLEX_FLOAT
4280 && !REG_CAN_CHANGE_MODE_P (xregno, xmode, ymode)(targetm.can_change_mode_class (xmode, ymode, (regclass_map[(
xregno)])))
)
4281 return -1;
4282
4283 /* We shouldn't simplify stack-related registers. */
4284 if ((!reload_completed || frame_pointer_needed((&x_rtl)->frame_pointer_needed))
4285 && xregno == FRAME_POINTER_REGNUM19)
4286 return -1;
4287
4288 if (FRAME_POINTER_REGNUM19 != ARG_POINTER_REGNUM16
4289 && xregno == ARG_POINTER_REGNUM16)
4290 return -1;
4291
4292 if (xregno == STACK_POINTER_REGNUM7
4293 /* We should convert hard stack register in LRA if it is
4294 possible. */
4295 && ! lra_in_progress)
4296 return -1;
4297
4298 /* Try to get the register offset. */
4299 subreg_get_info (xregno, xmode, offset, ymode, &info);
4300 if (!info.representable_p)
4301 return -1;
4302
4303 /* Make sure that the offsetted register value is in range. */
4304 yregno = xregno + info.offset;
4305 if (!HARD_REGISTER_NUM_P (yregno)((yregno) < 76))
4306 return -1;
4307
4308 /* See whether (reg:YMODE YREGNO) is valid.
4309
4310 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
4311 This is a kludge to work around how complex FP arguments are passed
4312 on IA-64 and should be fixed. See PR target/49226. */
4313 if (!targetm.hard_regno_mode_ok (yregno, ymode)
4314 && targetm.hard_regno_mode_ok (xregno, xmode))
4315 return -1;
4316
4317 return (int) yregno;
4318}
4319
4320/* Return the final regno that a subreg expression refers to. */
4321unsigned int
4322subreg_regno (const_rtx x)
4323{
4324 unsigned int ret;
4325 rtx subreg = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
4326 int regno = REGNO (subreg)(rhs_regno(subreg));
4327
4328 ret = regno + subreg_regno_offset (regno,
4329 GET_MODE (subreg)((machine_mode) (subreg)->mode),
4330 SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg),
4331 GET_MODE (x)((machine_mode) (x)->mode));
4332 return ret;
4333
4334}
4335
4336/* Return the number of registers that a subreg expression refers
4337 to. */
4338unsigned int
4339subreg_nregs (const_rtx x)
4340{
4341 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x))(rhs_regno((((x)->u.fld[0]).rt_rtx))), x);
4342}
4343
4344/* Return the number of registers that a subreg REG with REGNO
4345 expression refers to. This is a copy of the rtlanal.c:subreg_nregs
4346 changed so that the regno can be passed in. */
4347
4348unsigned int
4349subreg_nregs_with_regno (unsigned int regno, const_rtx x)
4350{
4351 struct subreg_info info;
4352 rtx subreg = SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx);
4353
4354 subreg_get_info (regno, GET_MODE (subreg)((machine_mode) (subreg)->mode), SUBREG_BYTE (x)(((x)->u.fld[1]).rt_subreg), GET_MODE (x)((machine_mode) (x)->mode),
4355 &info);
4356 return info.nregs;
4357}
4358
4359struct parms_set_data
4360{
4361 int nregs;
4362 HARD_REG_SET regs;
4363};
4364
4365/* Helper function for noticing stores to parameter registers. */
4366static void
4367parms_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED__attribute__ ((__unused__)), void *data)
4368{
4369 struct parms_set_data *const d = (struct parms_set_data *) data;
4370 if (REG_P (x)(((enum rtx_code) (x)->code) == REG) && REGNO (x)(rhs_regno(x)) < FIRST_PSEUDO_REGISTER76
4371 && TEST_HARD_REG_BIT (d->regs, REGNO (x)(rhs_regno(x))))
4372 {
4373 CLEAR_HARD_REG_BIT (d->regs, REGNO (x)(rhs_regno(x)));
4374 d->nregs--;
4375 }
4376}
4377
4378/* Look backward for first parameter to be loaded.
4379 Note that loads of all parameters will not necessarily be
4380 found if CSE has eliminated some of them (e.g., an argument
4381 to the outer function is passed down as a parameter).
4382 Do not skip BOUNDARY. */
4383rtx_insn *
4384find_first_parameter_load (rtx_insn *call_insn, rtx_insn *boundary)
4385{
4386 struct parms_set_data parm;
4387 rtx p;
4388 rtx_insn *before, *first_set;
4389
4390 /* Since different machines initialize their parameter registers
4391 in different orders, assume nothing. Collect the set of all
4392 parameter registers. */
4393 CLEAR_HARD_REG_SET (parm.regs);
4394 parm.nregs = 0;
4395 for (p = CALL_INSN_FUNCTION_USAGE (call_insn)(((call_insn)->u.fld[7]).rt_rtx); p; p = XEXP (p, 1)(((p)->u.fld[1]).rt_rtx))
4396 if (GET_CODE (XEXP (p, 0))((enum rtx_code) ((((p)->u.fld[0]).rt_rtx))->code) == USE
4397 && REG_P (XEXP (XEXP (p, 0), 0))(((enum rtx_code) (((((((p)->u.fld[0]).rt_rtx))->u.fld[
0]).rt_rtx))->code) == REG)
4398 && !STATIC_CHAIN_REG_P (XEXP (XEXP (p, 0), 0))(__extension__ ({ __typeof ((((((((p)->u.fld[0]).rt_rtx))->
u.fld[0]).rt_rtx))) const _rtx = ((((((((p)->u.fld[0]).rt_rtx
))->u.fld[0]).rt_rtx))); if (((enum rtx_code) (_rtx)->code
) != REG) rtl_check_failed_flag ("STATIC_CHAIN_REG_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4398, __FUNCTION__); _rtx; })->jump)
)
4399 {
4400 gcc_assert (REGNO (XEXP (XEXP (p, 0), 0)) < FIRST_PSEUDO_REGISTER)((void)(!((rhs_regno(((((((p)->u.fld[0]).rt_rtx))->u.fld
[0]).rt_rtx))) < 76) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4400, __FUNCTION__), 0 : 0))
;
4401
4402 /* We only care about registers which can hold function
4403 arguments. */
4404 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p, 0), 0)))ix86_function_arg_regno_p ((rhs_regno(((((((p)->u.fld[0]).
rt_rtx))->u.fld[0]).rt_rtx))))
)
4405 continue;
4406
4407 SET_HARD_REG_BIT (parm.regs, REGNO (XEXP (XEXP (p, 0), 0))(rhs_regno(((((((p)->u.fld[0]).rt_rtx))->u.fld[0]).rt_rtx
)))
);
4408 parm.nregs++;
4409 }
4410 before = call_insn;
4411 first_set = call_insn;
4412
4413 /* Search backward for the first set of a register in this set. */
4414 while (parm.nregs && before != boundary)
4415 {
4416 before = PREV_INSN (before);
4417
4418 /* It is possible that some loads got CSEed from one call to
4419 another. Stop in that case. */
4420 if (CALL_P (before)(((enum rtx_code) (before)->code) == CALL_INSN))
4421 break;
4422
4423 /* Our caller needs either ensure that we will find all sets
4424 (in case code has not been optimized yet), or take care
4425 for possible labels in a way by setting boundary to preceding
4426 CODE_LABEL. */
4427 if (LABEL_P (before)(((enum rtx_code) (before)->code) == CODE_LABEL))
4428 {
4429 gcc_assert (before == boundary)((void)(!(before == boundary) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4429, __FUNCTION__), 0 : 0))
;
4430 break;
4431 }
4432
4433 if (INSN_P (before)(((((enum rtx_code) (before)->code) == INSN) || (((enum rtx_code
) (before)->code) == JUMP_INSN) || (((enum rtx_code) (before
)->code) == CALL_INSN)) || (((enum rtx_code) (before)->
code) == DEBUG_INSN))
)
4434 {
4435 int nregs_old = parm.nregs;
4436 note_stores (before, parms_set, &parm);
4437 /* If we found something that did not set a parameter reg,
4438 we're done. Do not keep going, as that might result
4439 in hoisting an insn before the setting of a pseudo
4440 that is used by the hoisted insn. */
4441 if (nregs_old != parm.nregs)
4442 first_set = before;
4443 else
4444 break;
4445 }
4446 }
4447 return first_set;
4448}
4449
4450/* Return true if we should avoid inserting code between INSN and preceding
4451 call instruction. */
4452
4453bool
4454keep_with_call_p (const rtx_insn *insn)
4455{
4456 rtx set;
4457
4458 if (INSN_P (insn)(((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN)) || (((enum rtx_code) (insn)->code) ==
DEBUG_INSN))
&& (set = single_set (insn)) != NULLnullptr)
4459 {
4460 if (REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
REG)
4461 && REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx))) < FIRST_PSEUDO_REGISTER76
4462 && fixed_regs(this_target_hard_regs->x_fixed_regs)[REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx)))]
4463 && general_operand (SET_SRC (set)(((set)->u.fld[1]).rt_rtx), VOIDmode((void) 0, E_VOIDmode)))
4464 return true;
4465 if (REG_P (SET_SRC (set))(((enum rtx_code) ((((set)->u.fld[1]).rt_rtx))->code) ==
REG)
4466 && targetm.calls.function_value_regno_p (REGNO (SET_SRC (set))(rhs_regno((((set)->u.fld[1]).rt_rtx))))
4467 && REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
REG)
4468 && REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx))) >= FIRST_PSEUDO_REGISTER76)
4469 return true;
4470 /* There may be a stack pop just after the call and before the store
4471 of the return register. Search for the actual store when deciding
4472 if we can break or not. */
4473 if (SET_DEST (set)(((set)->u.fld[0]).rt_rtx) == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]))
4474 {
4475 /* This CONST_CAST is okay because next_nonnote_insn just
4476 returns its argument and we assign it to a const_rtx
4477 variable. */
4478 const rtx_insn *i2
4479 = next_nonnote_insn (const_cast<rtx_insn *> (insn));
4480 if (i2 && keep_with_call_p (i2))
4481 return true;
4482 }
4483 }
4484 return false;
4485}
4486
4487/* Return true if LABEL is a target of JUMP_INSN. This applies only
4488 to non-complex jumps. That is, direct unconditional, conditional,
4489 and tablejumps, but not computed jumps or returns. It also does
4490 not apply to the fallthru case of a conditional jump. */
4491
4492bool
4493label_is_jump_target_p (const_rtx label, const rtx_insn *jump_insn)
4494{
4495 rtx tmp = JUMP_LABEL (jump_insn)(((jump_insn)->u.fld[7]).rt_rtx);
4496 rtx_jump_table_data *table;
4497
4498 if (label == tmp)
4499 return true;
4500
4501 if (tablejump_p (jump_insn, NULLnullptr, &table))
4502 {
4503 rtvec vec = table->get_labels ();
4504 int i, veclen = GET_NUM_ELEM (vec)((vec)->num_elem);
4505
4506 for (i = 0; i < veclen; ++i)
4507 if (XEXP (RTVEC_ELT (vec, i), 0)(((((vec)->elem[i]))->u.fld[0]).rt_rtx) == label)
4508 return true;
4509 }
4510
4511 if (find_reg_note (jump_insn, REG_LABEL_TARGET, label))
4512 return true;
4513
4514 return false;
4515}
4516
4517
4518/* Return an estimate of the cost of computing rtx X.
4519 One use is in cse, to decide which expression to keep in the hash table.
4520 Another is in rtl generation, to pick the cheapest way to multiply.
4521 Other uses like the latter are expected in the future.
4522
4523 X appears as operand OPNO in an expression with code OUTER_CODE.
4524 SPEED specifies whether costs optimized for speed or size should
4525 be returned. */
4526
4527int
4528rtx_cost (rtx x, machine_mode mode, enum rtx_code outer_code,
4529 int opno, bool speed)
4530{
4531 int i, j;
4532 enum rtx_code code;
4533 const char *fmt;
4534 int total;
4535 int factor;
4536 unsigned mode_size;
4537
4538 if (x == 0)
4539 return 0;
4540
4541 if (GET_CODE (x)((enum rtx_code) (x)->code) == SET)
4542 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4543 the mode for the factor. */
4544 mode = GET_MODE (SET_DEST (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);
4545 else if (GET_MODE (x)((machine_mode) (x)->mode) != VOIDmode((void) 0, E_VOIDmode))
4546 mode = GET_MODE (x)((machine_mode) (x)->mode);
4547
4548 mode_size = estimated_poly_value (GET_MODE_SIZE (mode));
4549
4550 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4551 many insns, taking N times as long. */
4552 factor = mode_size > UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
0) ? 8 : 4)
? mode_size / UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
0) ? 8 : 4)
: 1;
4553
4554 /* Compute the default costs of certain things.
4555 Note that targetm.rtx_costs can override the defaults. */
4556
4557 code = GET_CODE (x)((enum rtx_code) (x)->code);
4558 switch (code)
4559 {
4560 case MULT:
4561 /* Multiplication has time-complexity O(N*N), where N is the
4562 number of units (translated from digits) when using
4563 schoolbook long multiplication. */
4564 total = factor * factor * COSTS_N_INSNS (5)((5) * 4);
4565 break;
4566 case DIV:
4567 case UDIV:
4568 case MOD:
4569 case UMOD:
4570 /* Similarly, complexity for schoolbook long division. */
4571 total = factor * factor * COSTS_N_INSNS (7)((7) * 4);
4572 break;
4573 case USE:
4574 /* Used in combine.c as a marker. */
4575 total = 0;
4576 break;
4577 default:
4578 total = factor * COSTS_N_INSNS (1)((1) * 4);
4579 }
4580
4581 switch (code)
4582 {
4583 case REG:
4584 return 0;
4585
4586 case SUBREG:
4587 total = 0;
4588 /* If we can't tie these modes, make this expensive. The larger
4589 the mode, the more expensive it is. */
4590 if (!targetm.modes_tieable_p (mode, GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode)))
4591 return COSTS_N_INSNS (2 + factor)((2 + factor) * 4);
4592 break;
4593
4594 case TRUNCATE:
4595 if (targetm.modes_tieable_p (mode, GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode)))
4596 {
4597 total = 0;
4598 break;
4599 }
4600 /* FALLTHRU */
4601 default:
4602 if (targetm.rtx_costs (x, mode, outer_code, opno, &total, speed))
4603 return total;
4604 break;
4605 }
4606
4607 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4608 which is already in total. */
4609
4610 fmt = GET_RTX_FORMAT (code)(rtx_format[(int) (code)]);
4611 for (i = GET_RTX_LENGTH (code)(rtx_length[(int) (code)]) - 1; i >= 0; i--)
4612 if (fmt[i] == 'e')
4613 total += rtx_cost (XEXP (x, i)(((x)->u.fld[i]).rt_rtx), mode, code, i, speed);
4614 else if (fmt[i] == 'E')
4615 for (j = 0; j < XVECLEN (x, i)(((((x)->u.fld[i]).rt_rtvec))->num_elem); j++)
4616 total += rtx_cost (XVECEXP (x, i, j)(((((x)->u.fld[i]).rt_rtvec))->elem[j]), mode, code, i, speed);
4617
4618 return total;
4619}
4620
4621/* Fill in the structure C with information about both speed and size rtx
4622 costs for X, which is operand OPNO in an expression with code OUTER. */
4623
4624void
4625get_full_rtx_cost (rtx x, machine_mode mode, enum rtx_code outer, int opno,
4626 struct full_rtx_costs *c)
4627{
4628 c->speed = rtx_cost (x, mode, outer, opno, true);
4629 c->size = rtx_cost (x, mode, outer, opno, false);
4630}
4631
4632
4633/* Return cost of address expression X.
4634 Expect that X is properly formed address reference.
4635
4636 SPEED parameter specify whether costs optimized for speed or size should
4637 be returned. */
4638
4639int
4640address_cost (rtx x, machine_mode mode, addr_space_t as, bool speed)
4641{
4642 /* We may be asked for cost of various unusual addresses, such as operands
4643 of push instruction. It is not worthwhile to complicate writing
4644 of the target hook by such cases. */
4645
4646 if (!memory_address_addr_space_p (mode, x, as))
4647 return 1000;
4648
4649 return targetm.address_cost (x, mode, as, speed);
4650}
4651
4652/* If the target doesn't override, compute the cost as with arithmetic. */
4653
4654int
4655default_address_cost (rtx x, machine_mode, addr_space_t, bool speed)
4656{
4657 return rtx_cost (x, Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
, MEM, 0, speed);
4658}
4659
4660
4661unsigned HOST_WIDE_INTlong
4662nonzero_bits (const_rtx x, machine_mode mode)
4663{
4664 if (mode == VOIDmode((void) 0, E_VOIDmode))
4665 mode = GET_MODE (x)((machine_mode) (x)->mode);
4666 scalar_int_mode int_mode;
4667 if (!is_a <scalar_int_mode> (mode, &int_mode))
4668 return GET_MODE_MASK (mode)mode_mask_array[mode];
4669 return cached_nonzero_bits (x, int_mode, NULL_RTX(rtx) 0, VOIDmode((void) 0, E_VOIDmode), 0);
4670}
4671
4672unsigned int
4673num_sign_bit_copies (const_rtx x, machine_mode mode)
4674{
4675 if (mode == VOIDmode((void) 0, E_VOIDmode))
4676 mode = GET_MODE (x)((machine_mode) (x)->mode);
4677 scalar_int_mode int_mode;
4678 if (!is_a <scalar_int_mode> (mode, &int_mode))
4679 return 1;
4680 return cached_num_sign_bit_copies (x, int_mode, NULL_RTX(rtx) 0, VOIDmode((void) 0, E_VOIDmode), 0);
4681}
4682
4683/* Return true if nonzero_bits1 might recurse into both operands
4684 of X. */
4685
4686static inline bool
4687nonzero_bits_binary_arith_p (const_rtx x)
4688{
4689 if (!ARITHMETIC_P (x)(((rtx_class[(int) (((enum rtx_code) (x)->code))]) & (
~1)) == (RTX_COMM_ARITH & (~1)))
)
4690 return false;
4691 switch (GET_CODE (x)((enum rtx_code) (x)->code))
4692 {
4693 case AND:
4694 case XOR:
4695 case IOR:
4696 case UMIN:
4697 case UMAX:
4698 case SMIN:
4699 case SMAX:
4700 case PLUS:
4701 case MINUS:
4702 case MULT:
4703 case DIV:
4704 case UDIV:
4705 case MOD:
4706 case UMOD:
4707 return true;
4708 default:
4709 return false;
4710 }
4711}
4712
4713/* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4714 It avoids exponential behavior in nonzero_bits1 when X has
4715 identical subexpressions on the first or the second level. */
4716
4717static unsigned HOST_WIDE_INTlong
4718cached_nonzero_bits (const_rtx x, scalar_int_mode mode, const_rtx known_x,
4719 machine_mode known_mode,
4720 unsigned HOST_WIDE_INTlong known_ret)
4721{
4722 if (x == known_x && mode == known_mode)
4723 return known_ret;
4724
4725 /* Try to find identical subexpressions. If found call
4726 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4727 precomputed value for the subexpression as KNOWN_RET. */
4728
4729 if (nonzero_bits_binary_arith_p (x))
4730 {
4731 rtx x0 = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
4732 rtx x1 = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);
4733
4734 /* Check the first level. */
4735 if (x0 == x1)
4736 return nonzero_bits1 (x, mode, x0, mode,
4737 cached_nonzero_bits (x0, mode, known_x,
4738 known_mode, known_ret));
4739
4740 /* Check the second level. */
4741 if (nonzero_bits_binary_arith_p (x0)
4742 && (x1 == XEXP (x0, 0)(((x0)->u.fld[0]).rt_rtx) || x1 == XEXP (x0, 1)(((x0)->u.fld[1]).rt_rtx)))
4743 return nonzero_bits1 (x, mode, x1, mode,
4744 cached_nonzero_bits (x1, mode, known_x,
4745 known_mode, known_ret));
4746
4747 if (nonzero_bits_binary_arith_p (x1)
4748 && (x0 == XEXP (x1, 0)(((x1)->u.fld[0]).rt_rtx) || x0 == XEXP (x1, 1)(((x1)->u.fld[1]).rt_rtx)))
4749 return nonzero_bits1 (x, mode, x0, mode,
4750 cached_nonzero_bits (x0, mode, known_x,
4751 known_mode, known_ret));
4752 }
4753
4754 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
4755}
4756
4757/* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4758 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4759 is less useful. We can't allow both, because that results in exponential
4760 run time recursion. There is a nullstone testcase that triggered
4761 this. This macro avoids accidental uses of num_sign_bit_copies. */
4762#define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4763
4764/* Given an expression, X, compute which bits in X can be nonzero.
4765 We don't care about bits outside of those defined in MODE.
4766
4767 For most X this is simply GET_MODE_MASK (GET_MODE (X)), but if X is
4768 an arithmetic operation, we can do better. */
4769
4770static unsigned HOST_WIDE_INTlong
4771nonzero_bits1 (const_rtx x, scalar_int_mode mode, const_rtx known_x,
4772 machine_mode known_mode,
4773 unsigned HOST_WIDE_INTlong known_ret)
4774{
4775 unsigned HOST_WIDE_INTlong nonzero = GET_MODE_MASK (mode)mode_mask_array[mode];
4776 unsigned HOST_WIDE_INTlong inner_nz;
4777 enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
4778 machine_mode inner_mode;
4779 unsigned int inner_width;
4780 scalar_int_mode xmode;
4781
4782 unsigned int mode_width = GET_MODE_PRECISION (mode);
4783
4784 if (CONST_INT_P (x)(((enum rtx_code) (x)->code) == CONST_INT))
1
Assuming field 'code' is not equal to CONST_INT
2
Taking false branch
4785 {
4786 if (SHORT_IMMEDIATES_SIGN_EXTEND0
4787 && INTVAL (x)((x)->u.hwint[0]) > 0
4788 && mode_width < BITS_PER_WORD((8) * (((global_options.x_ix86_isa_flags & (1UL <<
1)) != 0) ? 8 : 4))
4789 && (UINTVAL (x)((unsigned long) ((x)->u.hwint[0])) & (HOST_WIDE_INT_1U1UL << (mode_width - 1))) != 0)
4790 return UINTVAL (x)((unsigned long) ((x)->u.hwint[0])) | (HOST_WIDE_INT_M1U-1UL << mode_width);
4791
4792 return UINTVAL (x)((unsigned long) ((x)->u.hwint[0]));
4793 }
4794
4795 if (!is_a <scalar_int_mode> (GET_MODE (x)((machine_mode) (x)->mode), &xmode))
3
Calling 'is_a<scalar_int_mode, scalar_int_mode>'
7
Returning from 'is_a<scalar_int_mode, scalar_int_mode>'
8
Taking false branch
4796 return nonzero;
4797 unsigned int xmode_width = GET_MODE_PRECISION (xmode);
4798
4799 /* If X is wider than MODE, use its mode instead. */
4800 if (xmode_width > mode_width)
9
Assuming 'xmode_width' is <= 'mode_width'
10
Taking false branch
4801 {
4802 mode = xmode;
4803 nonzero = GET_MODE_MASK (mode)mode_mask_array[mode];
4804 mode_width = xmode_width;
4805 }
4806
4807 if (mode_width > HOST_BITS_PER_WIDE_INT64)
11
Assuming 'mode_width' is <= HOST_BITS_PER_WIDE_INT
12
Taking false branch
4808 /* Our only callers in this case look for single bit values. So
4809 just return the mode mask. Those tests will then be false. */
4810 return nonzero;
4811
4812 /* If MODE is wider than X, but both are a single word for both the host
4813 and target machines, we can compute this from which bits of the object
4814 might be nonzero in its own mode, taking into account the fact that, on
4815 CISC machines, accessing an object in a wider mode generally causes the
4816 high-order bits to become undefined, so they are not known to be zero.
4817 We extend this reasoning to RISC machines for operations that might not
4818 operate on the full registers. */
4819 if (mode_width > xmode_width
13
Assuming 'mode_width' is <= 'xmode_width'
4820 && xmode_width <= BITS_PER_WORD((8) * (((global_options.x_ix86_isa_flags & (1UL <<
1)) != 0) ? 8 : 4))
4821 && xmode_width <= HOST_BITS_PER_WIDE_INT64
4822 && !(WORD_REGISTER_OPERATIONS0 && word_register_operation_p (x)))
4823 {
4824 nonzero &= cached_nonzero_bits (x, xmode,
4825 known_x, known_mode, known_ret);
4826 nonzero |= GET_MODE_MASK (mode)mode_mask_array[mode] & ~GET_MODE_MASK (xmode)mode_mask_array[xmode];
4827 return nonzero;
4828 }
4829
4830 /* Please keep nonzero_bits_binary_arith_p above in sync with
4831 the code in the switch below. */
4832 switch (code)
14
Control jumps to 'case POPCOUNT:' at line 5179
4833 {
4834 case REG:
4835#if defined(POINTERS_EXTEND_UNSIGNED1)
4836 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4837 all the bits above ptr_mode are known to be zero. */
4838 /* As we do not know which address space the pointer is referring to,
4839 we can do this only if the target does not support different pointer
4840 or address modes depending on the address space. */
4841 if (target_default_pointer_address_modes_p ()
4842 && POINTERS_EXTEND_UNSIGNED1
4843 && xmode == Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
4844 && REG_POINTER (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag ("REG_POINTER"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 4844, __FUNCTION__); _rtx; })->frame_related)
4845 && !targetm.have_ptr_extend ())
4846 nonzero &= GET_MODE_MASK (ptr_mode)mode_mask_array[ptr_mode];
4847#endif
4848
4849 /* Include declared information about alignment of pointers. */
4850 /* ??? We don't properly preserve REG_POINTER changes across
4851 pointer-to-integer casts, so we can't trust it except for
4852 things that we know must be pointers. See execute/960116-1.c. */
4853 if ((x == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER])
4854 || x == frame_pointer_rtx((this_target_rtl->x_global_rtl)[GR_FRAME_POINTER])
4855 || x == arg_pointer_rtx((this_target_rtl->x_global_rtl)[GR_ARG_POINTER]))
4856 && REGNO_POINTER_ALIGN (REGNO (x))((&x_rtl)->emit.regno_pointer_align[(rhs_regno(x))]))
4857 {
4858 unsigned HOST_WIDE_INTlong alignment
4859 = REGNO_POINTER_ALIGN (REGNO (x))((&x_rtl)->emit.regno_pointer_align[(rhs_regno(x))]) / BITS_PER_UNIT(8);
4860
4861#ifdef PUSH_ROUNDING
4862 /* If PUSH_ROUNDING is defined, it is possible for the
4863 stack to be momentarily aligned only to that amount,
4864 so we pick the least alignment. */
4865 if (x == stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]) && PUSH_ARGS(((global_options.x_target_flags & (1U << 19)) == 0
) && !((((global_options.x_target_flags & (1U <<
3)) != 0) && optimize_function_for_speed_p ((cfun + 0
))) || ((cfun + 0)->machine->func_type != TYPE_NORMAL &&
(&x_rtl)->stack_realign_needed) || ((global_options.x_target_flags
& (1U << 25)) != 0) || (((global_options.x_ix86_isa_flags
& (1UL << 1)) != 0) && ix86_cfun_abi () ==
MS_ABI) || (0 && (&x_rtl)->profile)))
)
4866 {
4867 poly_uint64 rounded_1 = PUSH_ROUNDING (poly_int64 (1))ix86_push_rounding (poly_int64 (1));
4868 alignment = MIN (known_alignment (rounded_1), alignment)((known_alignment (rounded_1)) < (alignment) ? (known_alignment
(rounded_1)) : (alignment))
;
4869 }
4870#endif
4871
4872 nonzero &= ~(alignment - 1);
4873 }
4874
4875 {
4876 unsigned HOST_WIDE_INTlong nonzero_for_hook = nonzero;
4877 rtx new_rtx = rtl_hooks.reg_nonzero_bits (x, xmode, mode,
4878 &nonzero_for_hook);
4879
4880 if (new_rtx)
4881 nonzero_for_hook &= cached_nonzero_bits (new_rtx, mode, known_x,
4882 known_mode, known_ret);
4883
4884 return nonzero_for_hook;
4885 }
4886
4887 case MEM:
4888 /* In many, if not most, RISC machines, reading a byte from memory
4889 zeros the rest of the register. Noticing that fact saves a lot
4890 of extra zero-extends. */
4891 if (load_extend_op (xmode) == ZERO_EXTEND)
4892 nonzero &= GET_MODE_MASK (xmode)mode_mask_array[xmode];
4893 break;
4894
4895 case EQ: case NE:
4896 case UNEQ: case LTGT:
4897 case GT: case GTU: case UNGT:
4898 case LT: case LTU: case UNLT:
4899 case GE: case GEU: case UNGE:
4900 case LE: case LEU: case UNLE:
4901 case UNORDERED: case ORDERED:
4902 /* If this produces an integer result, we know which bits are set.
4903 Code here used to clear bits outside the mode of X, but that is
4904 now done above. */
4905 /* Mind that MODE is the mode the caller wants to look at this
4906 operation in, and not the actual operation mode. We can wind
4907 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4908 that describes the results of a vector compare. */
4909 if (GET_MODE_CLASS (xmode)((enum mode_class) mode_class[xmode]) == MODE_INT
4910 && mode_width <= HOST_BITS_PER_WIDE_INT64)
4911 nonzero = STORE_FLAG_VALUE1;
4912 break;
4913
4914 case NEG:
4915#if 0
4916 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4917 and num_sign_bit_copies. */
4918 if (num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), xmode) == xmode_width)
4919 nonzero = 1;
4920#endif
4921
4922 if (xmode_width < mode_width)
4923 nonzero |= (GET_MODE_MASK (mode)mode_mask_array[mode] & ~GET_MODE_MASK (xmode)mode_mask_array[xmode]);
4924 break;
4925
4926 case ABS:
4927#if 0
4928 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4929 and num_sign_bit_copies. */
4930 if (num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), xmode) == xmode_width)
4931 nonzero = 1;
4932#endif
4933 break;
4934
4935 case TRUNCATE:
4936 nonzero &= (cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
4937 known_x, known_mode, known_ret)
4938 & GET_MODE_MASK (mode)mode_mask_array[mode]);
4939 break;
4940
4941 case ZERO_EXTEND:
4942 nonzero &= cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
4943 known_x, known_mode, known_ret);
4944 if (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode) != VOIDmode((void) 0, E_VOIDmode))
4945 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)))mode_mask_array[((machine_mode) ((((x)->u.fld[0]).rt_rtx))
->mode)]
;
4946 break;
4947
4948 case SIGN_EXTEND:
4949 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4950 Otherwise, show all the bits in the outer mode but not the inner
4951 may be nonzero. */
4952 inner_nz = cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
4953 known_x, known_mode, known_ret);
4954 if (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode) != VOIDmode((void) 0, E_VOIDmode))
4955 {
4956 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)))mode_mask_array[((machine_mode) ((((x)->u.fld[0]).rt_rtx))
->mode)]
;
4957 if (val_signbit_known_set_p (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode), inner_nz))
4958 inner_nz |= (GET_MODE_MASK (mode)mode_mask_array[mode]
4959 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))mode_mask_array[((machine_mode) ((((x)->u.fld[0]).rt_rtx))
->mode)]
);
4960 }
4961
4962 nonzero &= inner_nz;
4963 break;
4964
4965 case AND:
4966 nonzero &= cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
4967 known_x, known_mode, known_ret)
4968 & cached_nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
4969 known_x, known_mode, known_ret);
4970 break;
4971
4972 case XOR: case IOR:
4973 case UMIN: case UMAX: case SMIN: case SMAX:
4974 {
4975 unsigned HOST_WIDE_INTlong nonzero0
4976 = cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
4977 known_x, known_mode, known_ret);
4978
4979 /* Don't call nonzero_bits for the second time if it cannot change
4980 anything. */
4981 if ((nonzero & nonzero0) != nonzero)
4982 nonzero &= nonzero0
4983 | cached_nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
4984 known_x, known_mode, known_ret);
4985 }
4986 break;
4987
4988 case PLUS: case MINUS:
4989 case MULT:
4990 case DIV: case UDIV:
4991 case MOD: case UMOD:
4992 /* We can apply the rules of arithmetic to compute the number of
4993 high- and low-order zero bits of these operations. We start by
4994 computing the width (position of the highest-order nonzero bit)
4995 and the number of low-order zero bits for each value. */
4996 {
4997 unsigned HOST_WIDE_INTlong nz0
4998 = cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
4999 known_x, known_mode, known_ret);
5000 unsigned HOST_WIDE_INTlong nz1
5001 = cached_nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
5002 known_x, known_mode, known_ret);
5003 int sign_index = xmode_width - 1;
5004 int width0 = floor_log2 (nz0) + 1;
5005 int width1 = floor_log2 (nz1) + 1;
5006 int low0 = ctz_or_zero (nz0);
5007 int low1 = ctz_or_zero (nz1);
5008 unsigned HOST_WIDE_INTlong op0_maybe_minusp
5009 = nz0 & (HOST_WIDE_INT_1U1UL << sign_index);
5010 unsigned HOST_WIDE_INTlong op1_maybe_minusp
5011 = nz1 & (HOST_WIDE_INT_1U1UL << sign_index);
5012 unsigned int result_width = mode_width;
5013 int result_low = 0;
5014
5015 switch (code)
5016 {
5017 case PLUS:
5018 result_width = MAX (width0, width1)((width0) > (width1) ? (width0) : (width1)) + 1;
5019 result_low = MIN (low0, low1)((low0) < (low1) ? (low0) : (low1));
5020 break;
5021 case MINUS:
5022 result_low = MIN (low0, low1)((low0) < (low1) ? (low0) : (low1));
5023 break;
5024 case MULT:
5025 result_width = width0 + width1;
5026 result_low = low0 + low1;
5027 break;
5028 case DIV:
5029 if (width1 == 0)
5030 break;
5031 if (!op0_maybe_minusp && !op1_maybe_minusp)
5032 result_width = width0;
5033 break;
5034 case UDIV:
5035 if (width1 == 0)
5036 break;
5037 result_width = width0;
5038 break;
5039 case MOD:
5040 if (width1 == 0)
5041 break;
5042 if (!op0_maybe_minusp && !op1_maybe_minusp)
5043 result_width = MIN (width0, width1)((width0) < (width1) ? (width0) : (width1));
5044 result_low = MIN (low0, low1)((low0) < (low1) ? (low0) : (low1));
5045 break;
5046 case UMOD:
5047 if (width1 == 0)
5048 break;
5049 result_width = MIN (width0, width1)((width0) < (width1) ? (width0) : (width1));
5050 result_low = MIN (low0, low1)((low0) < (low1) ? (low0) : (low1));
5051 break;
5052 default:
5053 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 5053, __FUNCTION__))
;
5054 }
5055
5056 if (result_width < mode_width)
5057 nonzero &= (HOST_WIDE_INT_1U1UL << result_width) - 1;
5058
5059 if (result_low > 0)
5060 nonzero &= ~((HOST_WIDE_INT_1U1UL << result_low) - 1);
5061 }
5062 break;
5063
5064 case ZERO_EXTRACT:
5065 if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
5066 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) < HOST_BITS_PER_WIDE_INT64)
5067 nonzero &= (HOST_WIDE_INT_1U1UL << INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0])) - 1;
5068 break;
5069
5070 case SUBREG:
5071 /* If this is a SUBREG formed for a promoted variable that has
5072 been zero-extended, we know that at least the high-order bits
5073 are zero, though others might be too. */
5074 if (SUBREG_PROMOTED_VAR_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag (
"SUBREG_PROMOTED", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 5074, __FUNCTION__); _rtx; })->in_struct)
&& SUBREG_PROMOTED_UNSIGNED_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag (
"SUBREG_PROMOTED_UNSIGNED_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 5074, __FUNCTION__); _rtx; })->volatil)
)
5075 nonzero = GET_MODE_MASK (xmode)mode_mask_array[xmode]
5076 & cached_nonzero_bits (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), xmode,
5077 known_x, known_mode, known_ret);
5078
5079 /* If the inner mode is a single word for both the host and target
5080 machines, we can compute this from which bits of the inner
5081 object might be nonzero. */
5082 inner_mode = GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode);
5083 if (GET_MODE_PRECISION (inner_mode).is_constant (&inner_width)
5084 && inner_width <= BITS_PER_WORD((8) * (((global_options.x_ix86_isa_flags & (1UL <<
1)) != 0) ? 8 : 4))
5085 && inner_width <= HOST_BITS_PER_WIDE_INT64)
5086 {
5087 nonzero &= cached_nonzero_bits (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), mode,
5088 known_x, known_mode, known_ret);
5089
5090 /* On a typical CISC machine, accessing an object in a wider mode
5091 causes the high-order bits to become undefined. So they are
5092 not known to be zero.
5093
5094 On a typical RISC machine, we only have to worry about the way
5095 loads are extended. Otherwise, if we get a reload for the inner
5096 part, it may be loaded from the stack, and then we may lose all
5097 the zero bits that existed before the store to the stack. */
5098 rtx_code extend_op;
5099 if ((!WORD_REGISTER_OPERATIONS0
5100 || ((extend_op = load_extend_op (inner_mode)) == SIGN_EXTEND
5101 ? val_signbit_known_set_p (inner_mode, nonzero)
5102 : extend_op != ZERO_EXTEND)
5103 || !MEM_P (SUBREG_REG (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == MEM
)
)
5104 && xmode_width > inner_width)
5105 nonzero
5106 |= (GET_MODE_MASK (GET_MODE (x))mode_mask_array[((machine_mode) (x)->mode)] & ~GET_MODE_MASK (inner_mode)mode_mask_array[inner_mode]);
5107 }
5108 break;
5109
5110 case ASHIFT:
5111 case ASHIFTRT:
5112 case LSHIFTRT:
5113 case ROTATE:
5114 case ROTATERT:
5115 /* The nonzero bits are in two classes: any bits within MODE
5116 that aren't in xmode are always significant. The rest of the
5117 nonzero bits are those that are significant in the operand of
5118 the shift when shifted the appropriate number of bits. This
5119 shows that high-order bits are cleared by the right shift and
5120 low-order bits by left shifts. */
5121 if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
5122 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) >= 0
5123 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) < HOST_BITS_PER_WIDE_INT64
5124 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) < xmode_width)
5125 {
5126 int count = INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]);
5127 unsigned HOST_WIDE_INTlong mode_mask = GET_MODE_MASK (xmode)mode_mask_array[xmode];
5128 unsigned HOST_WIDE_INTlong op_nonzero
5129 = cached_nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
5130 known_x, known_mode, known_ret);
5131 unsigned HOST_WIDE_INTlong inner = op_nonzero & mode_mask;
5132 unsigned HOST_WIDE_INTlong outer = 0;
5133
5134 if (mode_width > xmode_width)
5135 outer = (op_nonzero & nonzero & ~mode_mask);
5136
5137 switch (code)
5138 {
5139 case ASHIFT:
5140 inner <<= count;
5141 break;
5142
5143 case LSHIFTRT:
5144 inner >>= count;
5145 break;
5146
5147 case ASHIFTRT:
5148 inner >>= count;
5149
5150 /* If the sign bit may have been nonzero before the shift, we
5151 need to mark all the places it could have been copied to
5152 by the shift as possibly nonzero. */
5153 if (inner & (HOST_WIDE_INT_1U1UL << (xmode_width - 1 - count)))
5154 inner |= (((HOST_WIDE_INT_1U1UL << count) - 1)
5155 << (xmode_width - count));
5156 break;
5157
5158 case ROTATE:
5159 inner = (inner << (count % xmode_width)
5160 | (inner >> (xmode_width - (count % xmode_width))))
5161 & mode_mask;
5162 break;
5163
5164 case ROTATERT:
5165 inner = (inner >> (count % xmode_width)
5166 | (inner << (xmode_width - (count % xmode_width))))
5167 & mode_mask;
5168 break;
5169
5170 default:
5171 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 5171, __FUNCTION__))
;
5172 }
5173
5174 nonzero &= (outer | inner);
5175 }
5176 break;
5177
5178 case FFS:
5179 case POPCOUNT:
5180 /* This is at most the number of bits in the mode. */
5181 nonzero = ((unsigned HOST_WIDE_INTlong) 2 << (floor_log2 (mode_width))) - 1;
15
Calling 'floor_log2'
17
Returning from 'floor_log2'
18
The result of the left shift is undefined because the right operand is negative
5182 break;
5183
5184 case CLZ:
5185 /* If CLZ has a known value at zero, then the nonzero bits are
5186 that value, plus the number of bits in the mode minus one. */
5187 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero)((nonzero) = GET_MODE_BITSIZE (mode), ((global_options.x_ix86_isa_flags
& (1UL << 35)) != 0) ? 2 : 0)
)
5188 nonzero
5189 |= (HOST_WIDE_INT_1U1UL << (floor_log2 (mode_width))) - 1;
5190 else
5191 nonzero = -1;
5192 break;
5193
5194 case CTZ:
5195 /* If CTZ has a known value at zero, then the nonzero bits are
5196 that value, plus the number of bits in the mode minus one. */
5197 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero)((nonzero) = GET_MODE_BITSIZE (mode), ((global_options.x_ix86_isa_flags
& (1UL << 23)) != 0) ? 2 : 0)
)
5198 nonzero
5199 |= (HOST_WIDE_INT_1U1UL << (floor_log2 (mode_width))) - 1;
5200 else
5201 nonzero = -1;
5202 break;
5203
5204 case CLRSB:
5205 /* This is at most the number of bits in the mode minus 1. */
5206 nonzero = (HOST_WIDE_INT_1U1UL << (floor_log2 (mode_width))) - 1;
5207 break;
5208
5209 case PARITY:
5210 nonzero = 1;
5211 break;
5212
5213 case IF_THEN_ELSE:
5214 {
5215 unsigned HOST_WIDE_INTlong nonzero_true
5216 = cached_nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
5217 known_x, known_mode, known_ret);
5218
5219 /* Don't call nonzero_bits for the second time if it cannot change
5220 anything. */
5221 if ((nonzero & nonzero_true) != nonzero)
5222 nonzero &= nonzero_true
5223 | cached_nonzero_bits (XEXP (x, 2)(((x)->u.fld[2]).rt_rtx), mode,
5224 known_x, known_mode, known_ret);
5225 }
5226 break;
5227
5228 default:
5229 break;
5230 }
5231
5232 return nonzero;
5233}
5234
5235/* See the macro definition above. */
5236#undef cached_num_sign_bit_copies
5237
5238
5239/* Return true if num_sign_bit_copies1 might recurse into both operands
5240 of X. */
5241
5242static inline bool
5243num_sign_bit_copies_binary_arith_p (const_rtx x)
5244{
5245 if (!ARITHMETIC_P (x)(((rtx_class[(int) (((enum rtx_code) (x)->code))]) & (
~1)) == (RTX_COMM_ARITH & (~1)))
)
5246 return false;
5247 switch (GET_CODE (x)((enum rtx_code) (x)->code))
5248 {
5249 case IOR:
5250 case AND:
5251 case XOR:
5252 case SMIN:
5253 case SMAX:
5254 case UMIN:
5255 case UMAX:
5256 case PLUS:
5257 case MINUS:
5258 case MULT:
5259 return true;
5260 default:
5261 return false;
5262 }
5263}
5264
5265/* The function cached_num_sign_bit_copies is a wrapper around
5266 num_sign_bit_copies1. It avoids exponential behavior in
5267 num_sign_bit_copies1 when X has identical subexpressions on the
5268 first or the second level. */
5269
5270static unsigned int
5271cached_num_sign_bit_copies (const_rtx x, scalar_int_mode mode,
5272 const_rtx known_x, machine_mode known_mode,
5273 unsigned int known_ret)
5274{
5275 if (x == known_x && mode == known_mode)
5276 return known_ret;
5277
5278 /* Try to find identical subexpressions. If found call
5279 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
5280 the precomputed value for the subexpression as KNOWN_RET. */
5281
5282 if (num_sign_bit_copies_binary_arith_p (x))
5283 {
5284 rtx x0 = XEXP (x, 0)(((x)->u.fld[0]).rt_rtx);
5285 rtx x1 = XEXP (x, 1)(((x)->u.fld[1]).rt_rtx);
5286
5287 /* Check the first level. */
5288 if (x0 == x1)
5289 return
5290 num_sign_bit_copies1 (x, mode, x0, mode,
5291 cached_num_sign_bit_copies (x0, mode, known_x,
5292 known_mode,
5293 known_ret));
5294
5295 /* Check the second level. */
5296 if (num_sign_bit_copies_binary_arith_p (x0)
5297 && (x1 == XEXP (x0, 0)(((x0)->u.fld[0]).rt_rtx) || x1 == XEXP (x0, 1)(((x0)->u.fld[1]).rt_rtx)))
5298 return
5299 num_sign_bit_copies1 (x, mode, x1, mode,
5300 cached_num_sign_bit_copies (x1, mode, known_x,
5301 known_mode,
5302 known_ret));
5303
5304 if (num_sign_bit_copies_binary_arith_p (x1)
5305 && (x0 == XEXP (x1, 0)(((x1)->u.fld[0]).rt_rtx) || x0 == XEXP (x1, 1)(((x1)->u.fld[1]).rt_rtx)))
5306 return
5307 num_sign_bit_copies1 (x, mode, x0, mode,
5308 cached_num_sign_bit_copies (x0, mode, known_x,
5309 known_mode,
5310 known_ret));
5311 }
5312
5313 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
5314}
5315
5316/* Return the number of bits at the high-order end of X that are known to
5317 be equal to the sign bit. X will be used in mode MODE. The returned
5318 value will always be between 1 and the number of bits in MODE. */
5319
5320static unsigned int
5321num_sign_bit_copies1 (const_rtx x, scalar_int_mode mode, const_rtx known_x,
5322 machine_mode known_mode,
5323 unsigned int known_ret)
5324{
5325 enum rtx_code code = GET_CODE (x)((enum rtx_code) (x)->code);
5326 unsigned int bitwidth = GET_MODE_PRECISION (mode);
5327 int num0, num1, result;
5328 unsigned HOST_WIDE_INTlong nonzero;
5329
5330 if (CONST_INT_P (x)(((enum rtx_code) (x)->code) == CONST_INT))
5331 {
5332 /* If the constant is negative, take its 1's complement and remask.
5333 Then see how many zero bits we have. */
5334 nonzero = UINTVAL (x)((unsigned long) ((x)->u.hwint[0])) & GET_MODE_MASK (mode)mode_mask_array[mode];
5335 if (bitwidth <= HOST_BITS_PER_WIDE_INT64
5336 && (nonzero & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0)
5337 nonzero = (~nonzero) & GET_MODE_MASK (mode)mode_mask_array[mode];
5338
5339 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
5340 }
5341
5342 scalar_int_mode xmode, inner_mode;
5343 if (!is_a <scalar_int_mode> (GET_MODE (x)((machine_mode) (x)->mode), &xmode))
5344 return 1;
5345
5346 unsigned int xmode_width = GET_MODE_PRECISION (xmode);
5347
5348 /* For a smaller mode, just ignore the high bits. */
5349 if (bitwidth < xmode_width)
5350 {
5351 num0 = cached_num_sign_bit_copies (x, xmode,
5352 known_x, known_mode, known_ret);
5353 return MAX (1, num0 - (int) (xmode_width - bitwidth))((1) > (num0 - (int) (xmode_width - bitwidth)) ? (1) : (num0
- (int) (xmode_width - bitwidth)))
;
5354 }
5355
5356 if (bitwidth > xmode_width)
5357 {
5358 /* If this machine does not do all register operations on the entire
5359 register and MODE is wider than the mode of X, we can say nothing
5360 at all about the high-order bits. We extend this reasoning to RISC
5361 machines for operations that might not operate on full registers. */
5362 if (!(WORD_REGISTER_OPERATIONS0 && word_register_operation_p (x)))
5363 return 1;
5364
5365 /* Likewise on machines that do, if the mode of the object is smaller
5366 than a word and loads of that size don't sign extend, we can say
5367 nothing about the high order bits. */
5368 if (xmode_width < BITS_PER_WORD((8) * (((global_options.x_ix86_isa_flags & (1UL <<
1)) != 0) ? 8 : 4))
5369 && load_extend_op (xmode) != SIGN_EXTEND)
5370 return 1;
5371 }
5372
5373 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
5374 the code in the switch below. */
5375 switch (code)
5376 {
5377 case REG:
5378
5379#if defined(POINTERS_EXTEND_UNSIGNED1)
5380 /* If pointers extend signed and this is a pointer in Pmode, say that
5381 all the bits above ptr_mode are known to be sign bit copies. */
5382 /* As we do not know which address space the pointer is referring to,
5383 we can do this only if the target does not support different pointer
5384 or address modes depending on the address space. */
5385 if (target_default_pointer_address_modes_p ()
5386 && ! POINTERS_EXTEND_UNSIGNED1 && xmode == Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
5387 && mode == Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
&& REG_POINTER (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != REG) rtl_check_failed_flag ("REG_POINTER"
, _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 5387, __FUNCTION__); _rtx; })->frame_related)
5388 && !targetm.have_ptr_extend ())
5389 return GET_MODE_PRECISION (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)))
) - GET_MODE_PRECISION (ptr_mode) + 1;
5390#endif
5391
5392 {
5393 unsigned int copies_for_hook = 1, copies = 1;
5394 rtx new_rtx = rtl_hooks.reg_num_sign_bit_copies (x, xmode, mode,
5395 &copies_for_hook);
5396
5397 if (new_rtx)
5398 copies = cached_num_sign_bit_copies (new_rtx, mode, known_x,
5399 known_mode, known_ret);
5400
5401 if (copies > 1 || copies_for_hook > 1)
5402 return MAX (copies, copies_for_hook)((copies) > (copies_for_hook) ? (copies) : (copies_for_hook
))
;
5403
5404 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
5405 }
5406 break;
5407
5408 case MEM:
5409 /* Some RISC machines sign-extend all loads of smaller than a word. */
5410 if (load_extend_op (xmode) == SIGN_EXTEND)
5411 return MAX (1, ((int) bitwidth - (int) xmode_width + 1))((1) > (((int) bitwidth - (int) xmode_width + 1)) ? (1) : (
((int) bitwidth - (int) xmode_width + 1)))
;
5412 break;
5413
5414 case SUBREG:
5415 /* If this is a SUBREG for a promoted object that is sign-extended
5416 and we are looking at it in a wider mode, we know that at least the
5417 high-order bits are known to be sign bit copies. */
5418
5419 if (SUBREG_PROMOTED_VAR_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag (
"SUBREG_PROMOTED", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 5419, __FUNCTION__); _rtx; })->in_struct)
&& SUBREG_PROMOTED_SIGNED_P (x)(__extension__ ({ __typeof ((x)) const _rtx = ((x)); if (((enum
rtx_code) (_rtx)->code) != SUBREG) rtl_check_failed_flag (
"SUBREG_PROMOTED_SIGNED_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/rtlanal.c"
, 5419, __FUNCTION__); _rtx; })->unchanging)
)
5420 {
5421 num0 = cached_num_sign_bit_copies (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), mode,
5422 known_x, known_mode, known_ret);
5423 return MAX ((int) bitwidth - (int) xmode_width + 1, num0)(((int) bitwidth - (int) xmode_width + 1) > (num0) ? ((int
) bitwidth - (int) xmode_width + 1) : (num0))
;
5424 }
5425
5426 if (is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (x))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode), &inner_mode))
5427 {
5428 /* For a smaller object, just ignore the high bits. */
5429 if (bitwidth <= GET_MODE_PRECISION (inner_mode))
5430 {
5431 num0 = cached_num_sign_bit_copies (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), inner_mode,
5432 known_x, known_mode,
5433 known_ret);
5434 return MAX (1, num0 - (int) (GET_MODE_PRECISION (inner_mode)((1) > (num0 - (int) (GET_MODE_PRECISION (inner_mode) - bitwidth
)) ? (1) : (num0 - (int) (GET_MODE_PRECISION (inner_mode) - bitwidth
)))
5435 - bitwidth))((1) > (num0 - (int) (GET_MODE_PRECISION (inner_mode) - bitwidth
)) ? (1) : (num0 - (int) (GET_MODE_PRECISION (inner_mode) - bitwidth
)))
;
5436 }
5437
5438 /* For paradoxical SUBREGs on machines where all register operations
5439 affect the entire register, just look inside. Note that we are
5440 passing MODE to the recursive call, so the number of sign bit
5441 copies will remain relative to that mode, not the inner mode.
5442
5443 This works only if loads sign extend. Otherwise, if we get a
5444 reload for the inner part, it may be loaded from the stack, and
5445 then we lose all sign bit copies that existed before the store
5446 to the stack. */
5447 if (WORD_REGISTER_OPERATIONS0
5448 && load_extend_op (inner_mode) == SIGN_EXTEND
5449 && paradoxical_subreg_p (x)
5450 && MEM_P (SUBREG_REG (x))(((enum rtx_code) ((((x)->u.fld[0]).rt_rtx))->code) == MEM
)
)
5451 return cached_num_sign_bit_copies (SUBREG_REG (x)(((x)->u.fld[0]).rt_rtx), mode,
5452 known_x, known_mode, known_ret);
5453 }
5454 break;
5455
5456 case SIGN_EXTRACT:
5457 if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
)
5458 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)))((1) > ((int) bitwidth - (((((x)->u.fld[1]).rt_rtx))->
u.hwint[0])) ? (1) : ((int) bitwidth - (((((x)->u.fld[1]).
rt_rtx))->u.hwint[0])))
;
5459 break;
5460
5461 case SIGN_EXTEND:
5462 if (is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode), &inner_mode))
5463 return (bitwidth - GET_MODE_PRECISION (inner_mode)
5464 + cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), inner_mode,
5465 known_x, known_mode, known_ret));
5466 break;
5467
5468 case TRUNCATE:
5469 /* For a smaller object, just ignore the high bits. */
5470 inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0))((machine_mode) ((((x)->u.fld[0]).rt_rtx))->mode));
5471 num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), inner_mode,
5472 known_x, known_mode, known_ret);
5473 return MAX (1, (num0 - (int) (GET_MODE_PRECISION (inner_mode)((1) > ((num0 - (int) (GET_MODE_PRECISION (inner_mode) - bitwidth
))) ? (1) : ((num0 - (int) (GET_MODE_PRECISION (inner_mode) -
bitwidth))))
5474 - bitwidth)))((1) > ((num0 - (int) (GET_MODE_PRECISION (inner_mode) - bitwidth
))) ? (1) : ((num0 - (int) (GET_MODE_PRECISION (inner_mode) -
bitwidth))))
;
5475
5476 case NOT:
5477 return cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
5478 known_x, known_mode, known_ret);
5479
5480 case ROTATE: case ROTATERT:
5481 /* If we are rotating left by a number of bits less than the number
5482 of sign bit copies, we can just subtract that amount from the
5483 number. */
5484 if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
5485 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) >= 0
5486 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) < (int) bitwidth)
5487 {
5488 num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
5489 known_x, known_mode, known_ret);
5490 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))((1) > (num0 - (code == ROTATE ? (((((x)->u.fld[1]).rt_rtx
))->u.hwint[0]) : (int) bitwidth - (((((x)->u.fld[1]).rt_rtx
))->u.hwint[0]))) ? (1) : (num0 - (code == ROTATE ? (((((x
)->u.fld[1]).rt_rtx))->u.hwint[0]) : (int) bitwidth - (
((((x)->u.fld[1]).rt_rtx))->u.hwint[0]))))
5491 : (int) bitwidth - INTVAL (XEXP (x, 1))))((1) > (num0 - (code == ROTATE ? (((((x)->u.fld[1]).rt_rtx
))->u.hwint[0]) : (int) bitwidth - (((((x)->u.fld[1]).rt_rtx
))->u.hwint[0]))) ? (1) : (num0 - (code == ROTATE ? (((((x
)->u.fld[1]).rt_rtx))->u.hwint[0]) : (int) bitwidth - (
((((x)->u.fld[1]).rt_rtx))->u.hwint[0]))))
;
5492 }
5493 break;
5494
5495 case NEG:
5496 /* In general, this subtracts one sign bit copy. But if the value
5497 is known to be positive, the number of sign bit copies is the
5498 same as that of the input. Finally, if the input has just one bit
5499 that might be nonzero, all the bits are copies of the sign bit. */
5500 num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
5501 known_x, known_mode, known_ret);
5502 if (bitwidth > HOST_BITS_PER_WIDE_INT64)
5503 return num0 > 1 ? num0 - 1 : 1;
5504
5505 nonzero = nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode);
5506 if (nonzero == 1)
5507 return bitwidth;
5508
5509 if (num0 > 1
5510 && ((HOST_WIDE_INT_1U1UL << (bitwidth - 1)) & nonzero))
5511 num0--;
5512
5513 return num0;
5514
5515 case IOR: case AND: case XOR:
5516 case SMIN: case SMAX: case UMIN: case UMAX:
5517 /* Logical operations will preserve the number of sign-bit copies.
5518 MIN and MAX operations always return one of the operands. */
5519 num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
5520 known_x, known_mode, known_ret);
5521 num1 = cached_num_sign_bit_copies (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
5522 known_x, known_mode, known_ret);
5523
5524 /* If num1 is clearing some of the top bits then regardless of
5525 the other term, we are guaranteed to have at least that many
5526 high-order zero bits. */
5527 if (code == AND
5528 && num1 > 1
5529 && bitwidth <= HOST_BITS_PER_WIDE_INT64
5530 && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
5531 && (UINTVAL (XEXP (x, 1))((unsigned long) (((((x)->u.fld[1]).rt_rtx))->u.hwint[0
]))
5532 & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) == 0)
5533 return num1;
5534
5535 /* Similarly for IOR when setting high-order bits. */
5536 if (code == IOR
5537 && num1 > 1
5538 && bitwidth <= HOST_BITS_PER_WIDE_INT64
5539 && CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
5540 && (UINTVAL (XEXP (x, 1))((unsigned long) (((((x)->u.fld[1]).rt_rtx))->u.hwint[0
]))
5541 & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0)
5542 return num1;
5543
5544 return MIN (num0, num1)((num0) < (num1) ? (num0) : (num1));
5545
5546 case PLUS: case MINUS:
5547 /* For addition and subtraction, we can have a 1-bit carry. However,
5548 if we are subtracting 1 from a positive number, there will not
5549 be such a carry. Furthermore, if the positive number is known to
5550 be 0 or 1, we know the result is either -1 or 0. */
5551
5552 if (code == PLUS && XEXP (x, 1)(((x)->u.fld[1]).rt_rtx) == constm1_rtx(const_int_rtx[64 -1])
5553 && bitwidth <= HOST_BITS_PER_WIDE_INT64)
5554 {
5555 nonzero = nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode);
5556 if (((HOST_WIDE_INT_1U1UL << (bitwidth - 1)) & nonzero) == 0)
5557 return (nonzero == 1 || nonzero == 0 ? bitwidth
5558 : bitwidth - floor_log2 (nonzero) - 1);
5559 }
5560
5561 num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
5562 known_x, known_mode, known_ret);
5563 num1 = cached_num_sign_bit_copies (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
5564 known_x, known_mode, known_ret);
5565 result = MAX (1, MIN (num0, num1) - 1)((1) > (((num0) < (num1) ? (num0) : (num1)) - 1) ? (1) :
(((num0) < (num1) ? (num0) : (num1)) - 1))
;
5566
5567 return result;
5568
5569 case MULT:
5570 /* The number of bits of the product is the sum of the number of
5571 bits of both terms. However, unless one of the terms if known
5572 to be positive, we must allow for an additional bit since negating
5573 a negative number can remove one sign bit copy. */
5574
5575 num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
5576 known_x, known_mode, known_ret);
5577 num1 = cached_num_sign_bit_copies (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
5578 known_x, known_mode, known_ret);
5579
5580 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
5581 if (result > 0
5582 && (bitwidth > HOST_BITS_PER_WIDE_INT64
5583 || (((nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode)
5584 & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0)
5585 && ((nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode)
5586 & (HOST_WIDE_INT_1U1UL << (bitwidth - 1)))
5587 != 0))))
5588 result--;
5589
5590 return MAX (1, result)((1) > (result) ? (1) : (result));
5591
5592 case UDIV:
5593 /* The result must be <= the first operand. If the first operand
5594 has the high bit set, we know nothing about the number of sign
5595 bit copies. */
5596 if (bitwidth > HOST_BITS_PER_WIDE_INT64)
5597 return 1;
5598 else if ((nonzero_bits (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode)
5599 & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0)
5600 return 1;
5601 else
5602 return cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
5603 known_x, known_mode, known_ret);
5604
5605 case UMOD:
5606 /* The result must be <= the second operand. If the second operand
5607 has (or just might have) the high bit set, we know nothing about
5608 the number of sign bit copies. */
5609 if (bitwidth > HOST_BITS_PER_WIDE_INT64)
5610 return 1;
5611 else if ((nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode)
5612 & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0)
5613 return 1;
5614 else
5615 return cached_num_sign_bit_copies (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
5616 known_x, known_mode, known_ret);
5617
5618 case DIV:
5619 /* Similar to unsigned division, except that we have to worry about
5620 the case where the divisor is negative, in which case we have
5621 to add 1. */
5622 result = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
5623 known_x, known_mode, known_ret);
5624 if (result > 1
5625 && (bitwidth > HOST_BITS_PER_WIDE_INT64
5626 || (nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode)
5627 & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0))
5628 result--;
5629
5630 return result;
5631
5632 case MOD:
5633 result = cached_num_sign_bit_copies (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
5634 known_x, known_mode, known_ret);
5635 if (result > 1
5636 && (bitwidth > HOST_BITS_PER_WIDE_INT64
5637 || (nonzero_bits (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode)
5638 & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0))
5639 result--;
5640
5641 return result;
5642
5643 case ASHIFTRT:
5644 /* Shifts by a constant add to the number of bits equal to the
5645 sign bit. */
5646 num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
5647 known_x, known_mode, known_ret);
5648 if (CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
5649 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) > 0
5650 && INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) < xmode_width)
5651 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)))(((int) bitwidth) < (num0 + (((((x)->u.fld[1]).rt_rtx))
->u.hwint[0])) ? ((int) bitwidth) : (num0 + (((((x)->u.
fld[1]).rt_rtx))->u.hwint[0])))
;
5652
5653 return num0;
5654
5655 case ASHIFT:
5656 /* Left shifts destroy copies. */
5657 if (!CONST_INT_P (XEXP (x, 1))(((enum rtx_code) ((((x)->u.fld[1]).rt_rtx))->code) == CONST_INT
)
5658 || INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) < 0
5659 || INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) >= (int) bitwidth
5660 || INTVAL (XEXP (x, 1))(((((x)->u.fld[1]).rt_rtx))->u.hwint[0]) >= xmode_width)
5661 return 1;
5662
5663 num0 = cached_num_sign_bit_copies (XEXP (x, 0)(((x)->u.fld[0]).rt_rtx), mode,
5664 known_x, known_mode, known_ret);
5665 return MAX (1, num0 - INTVAL (XEXP (x, 1)))((1) > (num0 - (((((x)->u.fld[1]).rt_rtx))->u.hwint[
0])) ? (1) : (num0 - (((((x)->u.fld[1]).rt_rtx))->u.hwint
[0])))
;
5666
5667 case IF_THEN_ELSE:
5668 num0 = cached_num_sign_bit_copies (XEXP (x, 1)(((x)->u.fld[1]).rt_rtx), mode,
5669 known_x, known_mode, known_ret);
5670 num1 = cached_num_sign_bit_copies (XEXP (x, 2)(((x)->u.fld[2]).rt_rtx), mode,
5671 known_x, known_mode, known_ret);
5672 return MIN (num0, num1)((num0) < (num1) ? (num0) : (num1));
5673
5674 case EQ: case NE: case GE: case GT: case LE: case LT:
5675 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
5676 case GEU: case GTU: case LEU: case LTU:
5677 case UNORDERED: case ORDERED:
5678 /* If the constant is negative, take its 1's complement and remask.
5679 Then see how many zero bits we have. */
5680 nonzero = STORE_FLAG_VALUE1;
5681 if (bitwidth <= HOST_BITS_PER_WIDE_INT64
5682 && (nonzero & (HOST_WIDE_INT_1U1UL << (bitwidth - 1))) != 0)
5683 nonzero = (~nonzero) & GET_MODE_MASK (mode)mode_mask_array[mode];
5684