/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c

Bug Summary

File:	build/gcc/config/i386/i386-expand.c
Warning:	line 5032, column 15 Called function pointer is null (null dereference)
Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-unknown-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name i386-expand.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -fno-split-dwarf-inlining -debugger-tuning=gdb -resource-dir /usr/lib64/clang/11.0.0 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/10/../../../../include/c++/10 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/10/../../../../include/c++/10/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/10/../../../../include/c++/10/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib64/clang/11.0.0/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-error=format-diag -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -o /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2021-01-16-135054-17580-1/report-9Gr9jG.plist -x c++ /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c
1/* Copyright (C) 1988-2021 Free Software Foundation, Inc.

3This file is part of GCC.

5GCC is free software; you can redistribute it and/or modify
6it under the terms of the GNU General Public License as published by
7the Free Software Foundation; either version 3, or (at your option)
8any later version.

10GCC is distributed in the hope that it will be useful,
11but WITHOUT ANY WARRANTY; without even the implied warranty of
12MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13GNU General Public License for more details.

15You should have received a copy of the GNU General Public License
16along with GCC; see the file COPYING3.  If not see
17<http://www.gnu.org/licenses/>.  */

19#define IN_TARGET_CODE1 1

21#include "config.h"
22#include "system.h"
23#include "coretypes.h"
24#include "backend.h"
25#include "rtl.h"
26#include "tree.h"
27#include "memmodel.h"
28#include "gimple.h"
29#include "cfghooks.h"
30#include "cfgloop.h"
31#include "df.h"
32#include "tm_p.h"
33#include "stringpool.h"
34#include "expmed.h"
35#include "optabs.h"
36#include "regs.h"
37#include "emit-rtl.h"
38#include "recog.h"
39#include "cgraph.h"
40#include "diagnostic.h"
41#include "cfgbuild.h"
42#include "alias.h"
43#include "fold-const.h"
44#include "attribs.h"
45#include "calls.h"
46#include "stor-layout.h"
47#include "varasm.h"
48#include "output.h"
49#include "insn-attr.h"
50#include "flags.h"
51#include "except.h"
52#include "explow.h"
53#include "expr.h"
54#include "cfgrtl.h"
55#include "common/common-target.h"
56#include "langhooks.h"
57#include "reload.h"
58#include "gimplify.h"
59#include "dwarf2.h"
60#include "tm-constrs.h"
61#include "cselib.h"
62#include "sched-int.h"
63#include "opts.h"
64#include "tree-pass.h"
65#include "context.h"
66#include "pass_manager.h"
67#include "target-globals.h"
68#include "gimple-iterator.h"
69#include "tree-vectorizer.h"
70#include "shrink-wrap.h"
71#include "builtins.h"
72#include "rtl-iter.h"
73#include "tree-iterator.h"
74#include "dbgcnt.h"
75#include "case-cfn-macros.h"
76#include "dojump.h"
77#include "fold-const-call.h"
78#include "tree-vrp.h"
79#include "tree-ssanames.h"
80#include "selftest.h"
81#include "selftest-rtl.h"
82#include "print-rtl.h"
83#include "intl.h"
84#include "ifcvt.h"
85#include "symbol-summary.h"
86#include "ipa-prop.h"
87#include "ipa-fnsummary.h"
88#include "wide-int-bitmask.h"
89#include "tree-vector-builder.h"
90#include "debug.h"
91#include "dwarf2out.h"
92#include "i386-options.h"
93#include "i386-builtins.h"
94#include "i386-expand.h"

96/* Split one or more double-mode RTL references into pairs of half-mode
 references.  The RTL can be REG, offsettable MEM, integer constant, or
 CONST_DOUBLE.  "operands" is a pointer to an array of double-mode RTLs to
 split and "num" is its length.  lo_half and hi_half are output arrays
 that parallel "operands".  */

102void
103split_double_mode (machine_mode mode, rtx operands[],
   int num, rtx lo_half[], rtx hi_half[])
105{
machine_mode half_mode;
unsigned int byte;
rtx mem_op = NULL_RTX(rtx) 0;
int mem_num = 0;

switch (mode)
  {
  case E_TImode:
    half_mode = DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode));
    break;
  case E_DImode:
    half_mode = SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode));
    break;
  case E_P2HImode:
    half_mode = HImode(scalar_int_mode ((scalar_int_mode::from_int) E_HImode));
    break;
  case E_P2QImode:
    half_mode = QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode));
    break;
  default:
    gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 126, __FUNCTION__));
  }

byte = GET_MODE_SIZE (half_mode)((unsigned short) mode_to_bytes (half_mode).coeffs[0]);

while (num--)
  {
    rtx op = operands[num];

    /* simplify_subreg refuse to split volatile memory addresses,
       but we still have to handle it.  */
    if (MEM_P (op)(((enum rtx_code) (op)->code) == MEM))
{
 if (mem_op && rtx_equal_p (op, mem_op))
   {
     lo_half[num] = lo_half[mem_num];
     hi_half[num] = hi_half[mem_num];
   }
 else
   {
     mem_op = op;
     mem_num = num;
     lo_half[num] = adjust_address (op, half_mode, 0)adjust_address_1 (op, half_mode, 0, 1, 1, 0, 0);
     hi_half[num] = adjust_address (op, half_mode, byte)adjust_address_1 (op, half_mode, byte, 1, 1, 0, 0);
   }
}
    else
{
 lo_half[num] = simplify_gen_subreg (half_mode, op,
			      GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode)
			      ? mode : GET_MODE (op)((machine_mode) (op)->mode), 0);
 hi_half[num] = simplify_gen_subreg (half_mode, op,
			      GET_MODE (op)((machine_mode) (op)->mode) == VOIDmode((void) 0, E_VOIDmode)
			      ? mode : GET_MODE (op)((machine_mode) (op)->mode), byte);
}
  }
162}

164/* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
 for the target.  */

167void
168ix86_expand_clear (rtx dest)
169{
rtx tmp;

/* We play register width games, which are only valid after reload.  */
gcc_assert (reload_completed)((void)(!(reload_completed) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 173, __FUNCTION__), 0 : 0));

/* Avoid HImode and its attendant prefix byte.  */
if (GET_MODE_SIZE (GET_MODE (dest))((unsigned short) mode_to_bytes (((machine_mode) (dest)->mode
)).coeffs[0]) < 4)
  dest = gen_rtx_REG (SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), REGNO (dest)(rhs_regno(dest)));
tmp = gen_rtx_SET (dest, const0_rtx)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), (((const_int_rtx[64]))) );

if (!TARGET_USE_MOV0ix86_tune_features[X86_TUNE_USE_MOV0] || optimize_insn_for_size_p ())
  {
    rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG))gen_rtx_fmt_e_stat ((CLOBBER), ((((void) 0, E_VOIDmode))), ((
gen_rtx_REG (((void) 0, E_CCmode), 17))) );
    tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, tmp, clob))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, tmp, clob))) );
  }

emit_insn (tmp);
187}

189void
190ix86_expand_move (machine_mode mode, rtx operands[])
191{
rtx op0, op1;
rtx tmp, addend = NULL_RTX(rtx) 0;
enum tls_model model;

op0 = operands[0];
op1 = operands[1];

/* Avoid complex sets of likely spilled hard registers before reload.  */
if (!ix86_hardreg_mov_ok (op0, op1))
  {
    tmp = gen_reg_rtx (mode);
    operands[0] = tmp;
    ix86_expand_move (mode, operands);
    operands[0] = op0;
    operands[1] = tmp;
    op1 = tmp;
  }

switch (GET_CODE (op1)((enum rtx_code) (op1)->code))
  {
  case CONST:
    tmp = XEXP (op1, 0)(((op1)->u.fld[0]).rt_rtx);

    if (GET_CODE (tmp)((enum rtx_code) (tmp)->code) != PLUS
 || GET_CODE (XEXP (tmp, 0))((enum rtx_code) ((((tmp)->u.fld[0]).rt_rtx))->code) != SYMBOL_REF)
break;

    op1 = XEXP (tmp, 0)(((tmp)->u.fld[0]).rt_rtx);
    addend = XEXP (tmp, 1)(((tmp)->u.fld[1]).rt_rtx);
    /* FALLTHRU */

  case SYMBOL_REF:
    model = SYMBOL_REF_TLS_MODEL (op1)((enum tls_model) (((__extension__ ({ __typeof ((op1)) const _rtx
 = ((op1)); if (((enum rtx_code) (_rtx)->code) != SYMBOL_REF
) rtl_check_failed_flag ("SYMBOL_REF_FLAGS", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 224, __FUNCTION__); _rtx; }) ->u2.symbol_ref_flags) >>
 3) & 7));

    if (model)
op1 = legitimize_tls_address (op1, model, true);
    else if (ix86_force_load_from_GOT_p (op1))
{
 /* Load the external function address via GOT slot to avoid PLT.  */
 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op1),gen_rtx_fmt_Ei_stat ((UNSPEC), (((global_options.x_ix86_pmode
 == PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((gen_rtvec (1, op1))), (((((global_options.x_ix86_isa_flags
 & (1UL << 1)) != 0) ? UNSPEC_GOTPCREL : UNSPEC_GOT
))) )
		(TARGET_64BITgen_rtx_fmt_Ei_stat ((UNSPEC), (((global_options.x_ix86_pmode
 == PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((gen_rtvec (1, op1))), (((((global_options.x_ix86_isa_flags
 & (1UL << 1)) != 0) ? UNSPEC_GOTPCREL : UNSPEC_GOT
))) )
		 ? UNSPEC_GOTPCRELgen_rtx_fmt_Ei_stat ((UNSPEC), (((global_options.x_ix86_pmode
 == PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((gen_rtvec (1, op1))), (((((global_options.x_ix86_isa_flags
 & (1UL << 1)) != 0) ? UNSPEC_GOTPCREL : UNSPEC_GOT
))) )
		 : UNSPEC_GOT))gen_rtx_fmt_Ei_stat ((UNSPEC), (((global_options.x_ix86_pmode
 == PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((gen_rtvec (1, op1))), (((((global_options.x_ix86_isa_flags
 & (1UL << 1)) != 0) ? UNSPEC_GOTPCREL : UNSPEC_GOT
))) );
 op1 = gen_rtx_CONST (Pmode, op1)gen_rtx_fmt_e_stat ((CONST), (((global_options.x_ix86_pmode ==
 PMODE_DI ? (scalar_int_mode ((scalar_int_mode::from_int) E_DImode
)) : (scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
))), ((op1)) );
 op1 = gen_const_mem (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), op1);
 set_mem_alias_set (op1, ix86_GOT_alias_set ());
}
    else
{
 tmp = legitimize_pe_coff_symbol (op1, addend != NULL_RTX(rtx) 0);
 if (tmp)
   {
     op1 = tmp;
     if (!addend)
break;
   }
 else
   {
     op1 = operands[1];
     break;
   }
}

    if (addend)
{
 op1 = force_operand (op1, NULL_RTX(rtx) 0);
 op1 = expand_simple_binop (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), PLUS, op1, addend,
		     op0, 1, OPTAB_DIRECT);
}
    else
op1 = force_operand (op1, op0);

    if (op1 == op0)
return;

    op1 = convert_to_mode (mode, op1, 1);

  default:
    break;
  }

if ((flag_picglobal_options.x_flag_pic || MACHOPIC_INDIRECT0)
    && symbolic_operand (op1, mode))
  {
    if (TARGET_MACHO0 && !TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
))
{
278#if TARGET_MACHO0
 /* dynamic-no-pic */
 if (MACHOPIC_INDIRECT0)
   {
     rtx temp = (op0 && REG_P (op0)(((enum rtx_code) (op0)->code) == REG) && mode == Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))))
	 ? op0 : gen_reg_rtx (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))));
     op1 = machopic_indirect_data_reference (op1, temp);
     if (MACHOPIC_PURE0)
op1 = machopic_legitimize_pic_address (op1, mode,
				       temp == op1 ? 0 : temp);
   }
 if (op0 != op1 && GET_CODE (op0)((enum rtx_code) (op0)->code) != MEM)
   {
     rtx insn = gen_rtx_SET (op0, op1)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((op0))
, ((op1)) );
     emit_insn (insn);
     return;
   }
 if (GET_CODE (op0)((enum rtx_code) (op0)->code) == MEM)
   op1 = force_reg (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), op1);
 else
   {
     rtx temp = op0;
     if (GET_CODE (temp)((enum rtx_code) (temp)->code) != REG)
temp = gen_reg_rtx (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))));
     temp = legitimize_pic_address (op1, temp);
     if (temp == op0)
   return;
     op1 = temp;
   }
    /* dynamic-no-pic */
308#endif
}
    else
{
 if (MEM_P (op0)(((enum rtx_code) (op0)->code) == MEM))
   op1 = force_reg (mode, op1);
 else if (!(TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
) && x86_64_movabs_operand (op1, DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)))))
   {
     rtx reg = can_create_pseudo_p ()(!reload_in_progress && !reload_completed) ? NULL_RTX(rtx) 0 : op0;
     op1 = legitimize_pic_address (op1, reg);
     if (op0 == op1)
return;
     op1 = convert_to_mode (mode, op1, 1);
   }
}
  }
else
  {
    if (MEM_P (op0)(((enum rtx_code) (op0)->code) == MEM)
 && (PUSH_ROUNDING (GET_MODE_SIZE (mode))ix86_push_rounding (((unsigned short) mode_to_bytes (mode).coeffs
[0])) != GET_MODE_SIZE (mode)((unsigned short) mode_to_bytes (mode).coeffs[0])
     || !push_operand (op0, mode))
 && MEM_P (op1)(((enum rtx_code) (op1)->code) == MEM))
op1 = force_reg (mode, op1);

    if (push_operand (op0, mode)
 && ! general_no_elim_operand (op1, mode))
op1 = copy_to_mode_reg (mode, op1);

    /* Force large constants in 64bit compilation into register
to get them CSEed.  */
    if (can_create_pseudo_p ()(!reload_in_progress && !reload_completed)
 && (mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode))) && TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
)
 && immediate_operand (op1, mode)
 && !x86_64_zext_immediate_operand (op1, VOIDmode((void) 0, E_VOIDmode))
 && !register_operand (op0, mode)
 && optimizeglobal_options.x_optimize)
op1 = copy_to_mode_reg (mode, op1);

    if (can_create_pseudo_p ()(!reload_in_progress && !reload_completed)
 && CONST_DOUBLE_P (op1)(((enum rtx_code) (op1)->code) == CONST_DOUBLE))
{
 /* If we are loading a floating point constant to a register,
    force the value to memory now, since we'll get better code
    out the back end.  */

 op1 = validize_mem (force_const_mem (mode, op1));
 if (!register_operand (op0, mode))
   {
     rtx temp = gen_reg_rtx (mode);
     emit_insn (gen_rtx_SET (temp, op1)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((temp)
), ((op1)) ));
     emit_move_insn (op0, temp);
     return;
   }
}
  }

emit_insn (gen_rtx_SET (op0, op1)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((op0))
, ((op1)) ));
365}

367void
368ix86_expand_vector_move (machine_mode mode, rtx operands[])
369{
rtx op0 = operands[0], op1 = operands[1];
/* Use GET_MODE_BITSIZE instead of GET_MODE_ALIGNMENT for IA MCU
   psABI since the biggest alignment is 4 byte for IA MCU psABI.  */
unsigned int align = (TARGET_IAMCU((global_options.x_target_flags & (1U << 12)) != 0)
	? GET_MODE_BITSIZE (mode)((unsigned short) mode_to_bits (mode).coeffs[0])
	: GET_MODE_ALIGNMENT (mode)get_mode_alignment (mode));

if (push_operand (op0, VOIDmode((void) 0, E_VOIDmode)))
  op0 = emit_move_resolve_push (mode, op0);

/* Force constants other than zero into memory.  We do not know how
   the instructions used to build constants modify the upper 64 bits
   of the register, once we have that information we may be able
   to handle some of them more efficiently.  */
if (can_create_pseudo_p ()(!reload_in_progress && !reload_completed)
    && (CONSTANT_P (op1)((rtx_class[(int) (((enum rtx_code) (op1)->code))]) == RTX_CONST_OBJ
)
 || (SUBREG_P (op1)(((enum rtx_code) (op1)->code) == SUBREG)
     && CONSTANT_P (SUBREG_REG (op1))((rtx_class[(int) (((enum rtx_code) ((((op1)->u.fld[0]).rt_rtx
))->code))]) == RTX_CONST_OBJ)))
    && ((register_operand (op0, mode)
  && !standard_sse_constant_p (op1, mode))
 /* ix86_expand_vector_move_misalign() does not like constants.  */
 || (SSE_REG_MODE_P (mode)((mode) == ((void) 0, E_V1TImode) || (mode) == (scalar_int_mode
 ((scalar_int_mode::from_int) E_TImode)) || (mode) == ((void)
 0, E_V16QImode) || (mode) == (scalar_float_mode ((scalar_float_mode
::from_int) E_TFmode)) || (mode) == ((void) 0, E_V8HImode) ||
 (mode) == ((void) 0, E_V2DFmode) || (mode) == ((void) 0, E_V2DImode
) || (mode) == ((void) 0, E_V4SFmode) || (mode) == ((void) 0,
 E_V4SImode) || (mode) == ((void) 0, E_V32QImode) || (mode) ==
 ((void) 0, E_V16HImode) || (mode) == ((void) 0, E_V8SImode) ||
 (mode) == ((void) 0, E_V4DImode) || (mode) == ((void) 0, E_V8SFmode
) || (mode) == ((void) 0, E_V4DFmode) || (mode) == ((void) 0,
 E_V2TImode) || (mode) == ((void) 0, E_V8DImode) || (mode) ==
 ((void) 0, E_V64QImode) || (mode) == ((void) 0, E_V16SImode)
 || (mode) == ((void) 0, E_V32HImode) || (mode) == ((void) 0,
 E_V8DFmode) || (mode) == ((void) 0, E_V16SFmode))
     && MEM_P (op0)(((enum rtx_code) (op0)->code) == MEM)
     && MEM_ALIGN (op0)(get_mem_attrs (op0)->align) < align)))
  {
    if (SUBREG_P (op1)(((enum rtx_code) (op1)->code) == SUBREG))
{
 machine_mode imode = GET_MODE (SUBREG_REG (op1))((machine_mode) ((((op1)->u.fld[0]).rt_rtx))->mode);
 rtx r = force_const_mem (imode, SUBREG_REG (op1)(((op1)->u.fld[0]).rt_rtx));
 if (r)
   r = validize_mem (r);
 else
   r = force_reg (imode, SUBREG_REG (op1)(((op1)->u.fld[0]).rt_rtx));
 op1 = simplify_gen_subreg (mode, r, imode, SUBREG_BYTE (op1)(((op1)->u.fld[1]).rt_subreg));
}
    else
op1 = validize_mem (force_const_mem (mode, op1));
  }

/* We need to check memory alignment for SSE mode since attribute
   can make operands unaligned.  */
if (can_create_pseudo_p ()(!reload_in_progress && !reload_completed)
    && SSE_REG_MODE_P (mode)((mode) == ((void) 0, E_V1TImode) || (mode) == (scalar_int_mode
 ((scalar_int_mode::from_int) E_TImode)) || (mode) == ((void)
 0, E_V16QImode) || (mode) == (scalar_float_mode ((scalar_float_mode
::from_int) E_TFmode)) || (mode) == ((void) 0, E_V8HImode) ||
 (mode) == ((void) 0, E_V2DFmode) || (mode) == ((void) 0, E_V2DImode
) || (mode) == ((void) 0, E_V4SFmode) || (mode) == ((void) 0,
 E_V4SImode) || (mode) == ((void) 0, E_V32QImode) || (mode) ==
 ((void) 0, E_V16HImode) || (mode) == ((void) 0, E_V8SImode) ||
 (mode) == ((void) 0, E_V4DImode) || (mode) == ((void) 0, E_V8SFmode
) || (mode) == ((void) 0, E_V4DFmode) || (mode) == ((void) 0,
 E_V2TImode) || (mode) == ((void) 0, E_V8DImode) || (mode) ==
 ((void) 0, E_V64QImode) || (mode) == ((void) 0, E_V16SImode)
 || (mode) == ((void) 0, E_V32HImode) || (mode) == ((void) 0,
 E_V8DFmode) || (mode) == ((void) 0, E_V16SFmode))
    && ((MEM_P (op0)(((enum rtx_code) (op0)->code) == MEM) && (MEM_ALIGN (op0)(get_mem_attrs (op0)->align) < align))
 || (MEM_P (op1)(((enum rtx_code) (op1)->code) == MEM) && (MEM_ALIGN (op1)(get_mem_attrs (op1)->align) < align))))
  {
    rtx tmp[2];

    /* ix86_expand_vector_move_misalign() does not like both
arguments in memory.  */
    if (!register_operand (op0, mode)
 && !register_operand (op1, mode))
op1 = force_reg (mode, op1);

    tmp[0] = op0; tmp[1] = op1;
    ix86_expand_vector_move_misalign (mode, tmp);
    return;
  }

/* Make operand1 a register if it isn't already.  */
if (can_create_pseudo_p ()(!reload_in_progress && !reload_completed)
    && !register_operand (op0, mode)
    && !register_operand (op1, mode))
  {
    emit_move_insn (op0, force_reg (GET_MODE (op0)((machine_mode) (op0)->mode), op1));
    return;
  }

emit_insn (gen_rtx_SET (op0, op1)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((op0))
, ((op1)) ));
439}

441/* Split 32-byte AVX unaligned load and store if needed.  */

443static void
444ix86_avx256_split_vector_move_misalign (rtx op0, rtx op1)
445{
rtx m;
rtx (*extract) (rtx, rtx, rtx);
machine_mode mode;

if ((MEM_P (op1)(((enum rtx_code) (op1)->code) == MEM) && !TARGET_AVX256_SPLIT_UNALIGNED_LOAD((global_options.x_target_flags & (1U << 6)) != 0))
    || (MEM_P (op0)(((enum rtx_code) (op0)->code) == MEM) && !TARGET_AVX256_SPLIT_UNALIGNED_STORE((global_options.x_target_flags & (1U << 7)) != 0)))
  {
    emit_insn (gen_rtx_SET (op0, op1)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((op0))
, ((op1)) ));
    return;
  }

rtx orig_op0 = NULL_RTX(rtx) 0;
mode = GET_MODE (op0)((machine_mode) (op0)->mode);
switch (GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]))
  {
  case MODE_VECTOR_INT:
  case MODE_INT:
    if (mode != V32QImode((void) 0, E_V32QImode))
{
 if (!MEM_P (op0)(((enum rtx_code) (op0)->code) == MEM))
   {
     orig_op0 = op0;
     op0 = gen_reg_rtx (V32QImode((void) 0, E_V32QImode));
   }
 else
   op0 = gen_lowpartrtl_hooks.gen_lowpart (V32QImode((void) 0, E_V32QImode), op0);
 op1 = gen_lowpartrtl_hooks.gen_lowpart (V32QImode((void) 0, E_V32QImode), op1);
 mode = V32QImode((void) 0, E_V32QImode);
}
    break;
  case MODE_VECTOR_FLOAT:
    break;
  default:
    gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 479, __FUNCTION__));
  }

switch (mode)
  {
  default:
    gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 485, __FUNCTION__));
  case E_V32QImode:
    extract = gen_avx_vextractf128v32qi;
    mode = V16QImode((void) 0, E_V16QImode);
    break;
  case E_V8SFmode:
    extract = gen_avx_vextractf128v8sf;
    mode = V4SFmode((void) 0, E_V4SFmode);
    break;
  case E_V4DFmode:
    extract = gen_avx_vextractf128v4df;
    mode = V2DFmode((void) 0, E_V2DFmode);
    break;
  }

if (MEM_P (op1)(((enum rtx_code) (op1)->code) == MEM))
  {
    rtx r = gen_reg_rtx (mode);
    m = adjust_address (op1, mode, 0)adjust_address_1 (op1, mode, 0, 1, 1, 0, 0);
    emit_move_insn (r, m);
    m = adjust_address (op1, mode, 16)adjust_address_1 (op1, mode, 16, 1, 1, 0, 0);
    r = gen_rtx_VEC_CONCAT (GET_MODE (op0), r, m)gen_rtx_fmt_ee_stat ((VEC_CONCAT), ((((machine_mode) (op0)->
mode))), ((r)), ((m)) );
    emit_move_insn (op0, r);
  }
else if (MEM_P (op0)(((enum rtx_code) (op0)->code) == MEM))
  {
    m = adjust_address (op0, mode, 0)adjust_address_1 (op0, mode, 0, 1, 1, 0, 0);
    emit_insn (extract (m, op1, const0_rtx(const_int_rtx[64])));
    m = adjust_address (op0, mode, 16)adjust_address_1 (op0, mode, 16, 1, 1, 0, 0);
    emit_insn (extract (m, copy_rtx (op1), const1_rtx(const_int_rtx[64 +1])));
  }
else
  gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 517, __FUNCTION__));

if (orig_op0)
  emit_move_insn (orig_op0, gen_lowpartrtl_hooks.gen_lowpart (GET_MODE (orig_op0)((machine_mode) (orig_op0)->mode), op0));
521}

523/* Implement the movmisalign patterns for SSE.  Non-SSE modes go
 straight to ix86_expand_vector_move.  */
525/* Code generation for scalar reg-reg moves of single and double precision data:
   if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
     movaps reg, reg
   else
     movss reg, reg
   if (x86_sse_partial_reg_dependency == true)
     movapd reg, reg
   else
     movsd reg, reg

 Code generation for scalar loads of double precision data:
   if (x86_sse_split_regs == true)
     movlpd mem, reg      (gas syntax)
   else
     movsd mem, reg

 Code generation for unaligned packed loads of single precision data
 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
   if (x86_sse_unaligned_move_optimal)
     movups mem, reg

   if (x86_sse_partial_reg_dependency == true)
     {
       xorps  reg, reg
       movlps mem, reg
       movhps mem+8, reg
     }
   else
     {
       movlps mem, reg
       movhps mem+8, reg
     }

 Code generation for unaligned packed loads of double precision data
 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
   if (x86_sse_unaligned_move_optimal)
     movupd mem, reg

   if (x86_sse_split_regs == true)
     {
       movlpd mem, reg
       movhpd mem+8, reg
     }
   else
     {
       movsd  mem, reg
       movhpd mem+8, reg
     }
*/

575void
576ix86_expand_vector_move_misalign (machine_mode mode, rtx operands[])
577{
rtx op0, op1, m;

op0 = operands[0];
op1 = operands[1];

/* Use unaligned load/store for AVX512 or when optimizing for size.  */
if (GET_MODE_SIZE (mode)((unsigned short) mode_to_bytes (mode).coeffs[0]) == 64 || optimize_insn_for_size_p ())
  {
    emit_insn (gen_rtx_SET (op0, op1)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((op0))
, ((op1)) ));
    return;
  }

if (TARGET_AVX((global_options.x_ix86_isa_flags & (1UL << 8)) != 0
))
  {
    if (GET_MODE_SIZE (mode)((unsigned short) mode_to_bytes (mode).coeffs[0]) == 32)
ix86_avx256_split_vector_move_misalign (op0, op1);
    else
/* Always use 128-bit mov<mode>_internal pattern for AVX.  */
emit_insn (gen_rtx_SET (op0, op1)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((op0))
, ((op1)) ));
    return;
  }

if (TARGET_SSE_UNALIGNED_LOAD_OPTIMALix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL]
    || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMALix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL])
  {
    emit_insn (gen_rtx_SET (op0, op1)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((op0))
, ((op1)) ));
    return;
  }

/* ??? If we have typed data, then it would appear that using
   movdqu is the only way to get unaligned data loaded with
   integer type.  */
if (TARGET_SSE2((global_options.x_ix86_isa_flags & (1UL << 51)) !=
 0) && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) == MODE_VECTOR_INT)
  {
    emit_insn (gen_rtx_SET (op0, op1)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((op0))
, ((op1)) ));
    return;
  }

if (MEM_P (op1)(((enum rtx_code) (op1)->code) == MEM))
  {
    if (TARGET_SSE2((global_options.x_ix86_isa_flags & (1UL << 51)) !=
 0) && mode == V2DFmode((void) 0, E_V2DFmode))
      {
        rtx zero;

 /* When SSE registers are split into halves, we can avoid
    writing to the top half twice.  */
 if (TARGET_SSE_SPLIT_REGSix86_tune_features[X86_TUNE_SSE_SPLIT_REGS])
   {
     emit_clobber (op0);
     zero = op0;
   }
 else
   {
     /* ??? Not sure about the best option for the Intel chips.
 The following would seem to satisfy; the register is
 entirely cleared, breaking the dependency chain.  We
 then store to the upper half, with a dependency depth
 of one.  A rumor has it that Intel recommends two movsd
 followed by an unpacklpd, but this is unconfirmed.  And
 given that the dependency depth of the unpacklpd would
 still be one, I'm not sure why this would be better.  */
     zero = CONST0_RTX (V2DFmode)(const_tiny_rtx[0][(int) (((void) 0, E_V2DFmode))]);
   }

 m = adjust_address (op1, DFmode, 0)adjust_address_1 (op1, (scalar_float_mode ((scalar_float_mode
::from_int) E_DFmode)), 0, 1, 1, 0, 0);
 emit_insn (gen_sse2_loadlpd (op0, zero, m));
 m = adjust_address (op1, DFmode, 8)adjust_address_1 (op1, (scalar_float_mode ((scalar_float_mode
::from_int) E_DFmode)), 8, 1, 1, 0, 0);
 emit_insn (gen_sse2_loadhpd (op0, op0, m));
}
    else
      {
 rtx t;

 if (mode != V4SFmode((void) 0, E_V4SFmode))
   t = gen_reg_rtx (V4SFmode((void) 0, E_V4SFmode));
 else
   t = op0;
   
 if (TARGET_SSE_PARTIAL_REG_DEPENDENCYix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY])
   emit_move_insn (t, CONST0_RTX (V4SFmode)(const_tiny_rtx[0][(int) (((void) 0, E_V4SFmode))]));
 else
   emit_clobber (t);

 m = adjust_address (op1, V2SFmode, 0)adjust_address_1 (op1, ((void) 0, E_V2SFmode), 0, 1, 1, 0, 0);
 emit_insn (gen_sse_loadlps (t, t, m));
 m = adjust_address (op1, V2SFmode, 8)adjust_address_1 (op1, ((void) 0, E_V2SFmode), 8, 1, 1, 0, 0);
 emit_insn (gen_sse_loadhps (t, t, m));
 if (mode != V4SFmode((void) 0, E_V4SFmode))
   emit_move_insn (op0, gen_lowpartrtl_hooks.gen_lowpart (mode, t));
}
  }
else if (MEM_P (op0)(((enum rtx_code) (op0)->code) == MEM))
  {
    if (TARGET_SSE2((global_options.x_ix86_isa_flags & (1UL << 51)) !=
 0) && mode == V2DFmode((void) 0, E_V2DFmode))
{
 m = adjust_address (op0, DFmode, 0)adjust_address_1 (op0, (scalar_float_mode ((scalar_float_mode
::from_int) E_DFmode)), 0, 1, 1, 0, 0);
 emit_insn (gen_sse2_storelpd (m, op1));
 m = adjust_address (op0, DFmode, 8)adjust_address_1 (op0, (scalar_float_mode ((scalar_float_mode
::from_int) E_DFmode)), 8, 1, 1, 0, 0);
 emit_insn (gen_sse2_storehpd (m, op1));
}
    else
{
 if (mode != V4SFmode((void) 0, E_V4SFmode))
   op1 = gen_lowpartrtl_hooks.gen_lowpart (V4SFmode((void) 0, E_V4SFmode), op1);

 m = adjust_address (op0, V2SFmode, 0)adjust_address_1 (op0, ((void) 0, E_V2SFmode), 0, 1, 1, 0, 0);
 emit_insn (gen_sse_storelps (m, op1));
 m = adjust_address (op0, V2SFmode, 8)adjust_address_1 (op0, ((void) 0, E_V2SFmode), 8, 1, 1, 0, 0);
 emit_insn (gen_sse_storehps (m, copy_rtx (op1)));
}
  }
else
  gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 690, __FUNCTION__));
691}

693/* Move bits 64:95 to bits 32:63.  */

695void
696ix86_move_vector_high_sse_to_mmx (rtx op)
697{
rtx mask = gen_rtx_PARALLEL (VOIDmode,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (4, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (2)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (0)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (0))))) )
	       gen_rtvec (4, GEN_INT (0), GEN_INT (2),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (4, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (2)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (0)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (0))))) )
			  GEN_INT (0), GEN_INT (0)))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (4, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (2)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (0)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (0))))) );
rtx dest = lowpart_subreg (V4SImode((void) 0, E_V4SImode), op, GET_MODE (op)((machine_mode) (op)->mode));
op = gen_rtx_VEC_SELECT (V4SImode, dest, mask)gen_rtx_fmt_ee_stat ((VEC_SELECT), ((((void) 0, E_V4SImode)))
, ((dest)), ((mask)) );
rtx insn = gen_rtx_SET (dest, op)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((op)) );
emit_insn (insn);
705}

707/* Split MMX pack with signed/unsigned saturation with SSE/SSE2.  */

709void
710ix86_split_mmx_pack (rtx operands[], enum rtx_code code)
711{
rtx op0 = operands[0];
rtx op1 = operands[1];
rtx op2 = operands[2];

machine_mode dmode = GET_MODE (op0)((machine_mode) (op0)->mode);
machine_mode smode = GET_MODE (op1)((machine_mode) (op1)->mode);
machine_mode inner_dmode = GET_MODE_INNER (dmode)(mode_to_inner (dmode));
machine_mode inner_smode = GET_MODE_INNER (smode)(mode_to_inner (smode));

/* Get the corresponding SSE mode for destination.  */
int nunits = 16 / GET_MODE_SIZE (inner_dmode)((unsigned short) mode_to_bytes (inner_dmode).coeffs[0]);
machine_mode sse_dmode = mode_for_vector (GET_MODE_INNER (dmode)(mode_to_inner (dmode)),
			    nunits).require ();
machine_mode sse_half_dmode = mode_for_vector (GET_MODE_INNER (dmode)(mode_to_inner (dmode)),
				 nunits / 2).require ();

/* Get the corresponding SSE mode for source.  */
nunits = 16 / GET_MODE_SIZE (inner_smode)((unsigned short) mode_to_bytes (inner_smode).coeffs[0]);
machine_mode sse_smode = mode_for_vector (GET_MODE_INNER (smode)(mode_to_inner (smode)),
			    nunits).require ();

/* Generate SSE pack with signed/unsigned saturation.  */
rtx dest = lowpart_subreg (sse_dmode, op0, GET_MODE (op0)((machine_mode) (op0)->mode));
op1 = lowpart_subreg (sse_smode, op1, GET_MODE (op1)((machine_mode) (op1)->mode));
op2 = lowpart_subreg (sse_smode, op2, GET_MODE (op2)((machine_mode) (op2)->mode));

op1 = gen_rtx_fmt_e (code, sse_half_dmode, op1)gen_rtx_fmt_e_stat ((code), (sse_half_dmode), (op1) );
op2 = gen_rtx_fmt_e (code, sse_half_dmode, op2)gen_rtx_fmt_e_stat ((code), (sse_half_dmode), (op2) );
rtx insn = gen_rtx_SET (dest, gen_rtx_VEC_CONCAT (sse_dmode,gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((gen_rtx_fmt_ee_stat ((VEC_CONCAT), ((sse_dmode)), ((op1)
), ((op2)) ))) )
				    op1, op2))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((gen_rtx_fmt_ee_stat ((VEC_CONCAT), ((sse_dmode)), ((op1)
), ((op2)) ))) );
emit_insn (insn);

ix86_move_vector_high_sse_to_mmx (op0);
745}

747/* Split MMX punpcklXX/punpckhXX with SSE punpcklXX.  */

749void
750ix86_split_mmx_punpck (rtx operands[], bool high_p)
751{
rtx op0 = operands[0];
rtx op1 = operands[1];
rtx op2 = operands[2];
machine_mode mode = GET_MODE (op0)((machine_mode) (op0)->mode);
rtx mask;
/* The corresponding SSE mode.  */
machine_mode sse_mode, double_sse_mode;

switch (mode)
  {
  case E_V8QImode:
    sse_mode = V16QImode((void) 0, E_V16QImode);
    double_sse_mode = V32QImode((void) 0, E_V32QImode);
    mask = gen_rtx_PARALLEL (VOIDmode,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (16, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0
)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (16)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (17)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (18)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (19)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (4)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (20)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (5)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (21)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (6)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (22)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (7)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (23))))) )
	       gen_rtvec (16,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (16, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0
)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (16)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (17)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (18)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (19)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (4)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (20)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (5)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (21)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (6)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (22)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (7)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (23))))) )
			  GEN_INT (0), GEN_INT (16),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (16, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0
)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (16)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (17)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (18)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (19)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (4)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (20)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (5)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (21)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (6)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (22)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (7)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (23))))) )
			  GEN_INT (1), GEN_INT (17),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (16, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0
)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (16)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (17)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (18)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (19)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (4)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (20)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (5)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (21)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (6)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (22)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (7)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (23))))) )
			  GEN_INT (2), GEN_INT (18),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (16, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0
)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (16)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (17)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (18)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (19)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (4)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (20)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (5)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (21)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (6)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (22)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (7)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (23))))) )
			  GEN_INT (3), GEN_INT (19),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (16, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0
)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (16)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (17)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (18)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (19)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (4)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (20)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (5)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (21)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (6)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (22)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (7)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (23))))) )
			  GEN_INT (4), GEN_INT (20),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (16, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0
)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (16)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (17)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (18)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (19)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (4)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (20)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (5)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (21)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (6)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (22)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (7)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (23))))) )
			  GEN_INT (5), GEN_INT (21),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (16, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0
)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (16)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (17)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (18)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (19)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (4)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (20)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (5)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (21)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (6)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (22)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (7)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (23))))) )
			  GEN_INT (6), GEN_INT (22),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (16, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0
)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (16)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (17)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (18)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (19)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (4)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (20)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (5)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (21)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (6)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (22)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (7)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (23))))) )
			  GEN_INT (7), GEN_INT (23)))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (16, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0
)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (16)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (17)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (18)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (19)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (4)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (20)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (5)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (21)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (6)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (22)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (7)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (23))))) );
    break;

  case E_V4HImode:
    sse_mode = V8HImode((void) 0, E_V8HImode);
    double_sse_mode = V16HImode((void) 0, E_V16HImode);
    mask = gen_rtx_PARALLEL (VOIDmode,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (8, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (8)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (9)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode)
, (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (10)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (11))))) )
	       gen_rtvec (8,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (8, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (8)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (9)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode)
, (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (10)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (11))))) )
			  GEN_INT (0), GEN_INT (8),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (8, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (8)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (9)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode)
, (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (10)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (11))))) )
			  GEN_INT (1), GEN_INT (9),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (8, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (8)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (9)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode)
, (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (10)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (11))))) )
			  GEN_INT (2), GEN_INT (10),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (8, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (8)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (9)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode)
, (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (10)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (11))))) )
			  GEN_INT (3), GEN_INT (11)))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (8, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (8)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (9)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode)
, (2)), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (10)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (11))))) );
    break;

  case E_V2SImode:
    sse_mode = V4SImode((void) 0, E_V4SImode);
    double_sse_mode = V8SImode((void) 0, E_V8SImode);
    mask = gen_rtx_PARALLEL (VOIDmode,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (4, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (4)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (5))))) )
	       gen_rtvec (4,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (4, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (4)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (5))))) )
			  GEN_INT (0), GEN_INT (4),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (4, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (4)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (5))))) )
			  GEN_INT (1), GEN_INT (5)))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (4, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (4)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (1)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (5))))) );
    break;

  default:
    gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 798, __FUNCTION__));
  }

/* Generate SSE punpcklXX.  */
rtx dest = lowpart_subreg (sse_mode, op0, GET_MODE (op0)((machine_mode) (op0)->mode));
op1 = lowpart_subreg (sse_mode, op1, GET_MODE (op1)((machine_mode) (op1)->mode));
op2 = lowpart_subreg (sse_mode, op2, GET_MODE (op2)((machine_mode) (op2)->mode));

op1 = gen_rtx_VEC_CONCAT (double_sse_mode, op1, op2)gen_rtx_fmt_ee_stat ((VEC_CONCAT), ((double_sse_mode)), ((op1
)), ((op2)) );
op2 = gen_rtx_VEC_SELECT (sse_mode, op1, mask)gen_rtx_fmt_ee_stat ((VEC_SELECT), ((sse_mode)), ((op1)), ((mask
)) );
rtx insn = gen_rtx_SET (dest, op2)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((op2)) );
emit_insn (insn);

if (high_p)
  {
    /* Move bits 64:127 to bits 0:63.  */
    mask = gen_rtx_PARALLEL (VOIDmode,gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (4, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (2)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (0)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (0))))) )
	       gen_rtvec (4, GEN_INT (2), GEN_INT (3),gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (4, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (2)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (0)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (0))))) )
			  GEN_INT (0), GEN_INT (0)))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (4, gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (2)
), gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (3)), gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (0)), gen_rtx_CONST_INT (((void) 0,
 E_VOIDmode), (0))))) );
    dest = lowpart_subreg (V4SImode((void) 0, E_V4SImode), dest, GET_MODE (dest)((machine_mode) (dest)->mode));
    op1 = gen_rtx_VEC_SELECT (V4SImode, dest, mask)gen_rtx_fmt_ee_stat ((VEC_SELECT), ((((void) 0, E_V4SImode)))
, ((dest)), ((mask)) );
    insn = gen_rtx_SET (dest, op1)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((op1)) );
    emit_insn (insn);
  }
822}

824/* Helper function of ix86_fixup_binary_operands to canonicalize
 operand order.  Returns true if the operands should be swapped.  */

827static bool
828ix86_swap_binary_operands_p (enum rtx_code code, machine_mode mode,
	     rtx operands[])
830{
rtx dst = operands[0];
rtx src1 = operands[1];
rtx src2 = operands[2];

/* If the operation is not commutative, we can't do anything.  */
if (GET_RTX_CLASS (code)(rtx_class[(int) (code)]) != RTX_COMM_ARITH
    && GET_RTX_CLASS (code)(rtx_class[(int) (code)]) != RTX_COMM_COMPARE)
  return false;

/* Highest priority is that src1 should match dst.  */
if (rtx_equal_p (dst, src1))
  return false;
if (rtx_equal_p (dst, src2))
  return true;

/* Next highest priority is that immediate constants come second.  */
if (immediate_operand (src2, mode))
  return false;
if (immediate_operand (src1, mode))
  return true;

/* Lowest priority is that memory references should come second.  */
if (MEM_P (src2)(((enum rtx_code) (src2)->code) == MEM))
  return false;
if (MEM_P (src1)(((enum rtx_code) (src1)->code) == MEM))
  return true;

return false;
859}


862/* Fix up OPERANDS to satisfy ix86_binary_operator_ok.  Return the
 destination to use for the operation.  If different from the true
 destination in operands[0], a copy operation will be required.  */

866rtx
867ix86_fixup_binary_operands (enum rtx_code code, machine_mode mode,
	    rtx operands[])
869{
rtx dst = operands[0];
rtx src1 = operands[1];
rtx src2 = operands[2];

/* Canonicalize operand order.  */
if (ix86_swap_binary_operands_p (code, mode, operands))
  {
    /* It is invalid to swap operands of different modes.  */
    gcc_assert (GET_MODE (src1) == GET_MODE (src2))((void)(!(((machine_mode) (src1)->mode) == ((machine_mode)
 (src2)->mode)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 878, __FUNCTION__), 0 : 0));

    std::swap (src1, src2);
  }

/* Both source operands cannot be in memory.  */
if (MEM_P (src1)(((enum rtx_code) (src1)->code) == MEM) && MEM_P (src2)(((enum rtx_code) (src2)->code) == MEM))
  {
    /* Optimization: Only read from memory once.  */
    if (rtx_equal_p (src1, src2))
{
 src2 = force_reg (mode, src2);
 src1 = src2;
}
    else if (rtx_equal_p (dst, src1))
src2 = force_reg (mode, src2);
    else
src1 = force_reg (mode, src1);
  }

/* If the destination is memory, and we do not have matching source
   operands, do things in registers.  */
if (MEM_P (dst)(((enum rtx_code) (dst)->code) == MEM) && !rtx_equal_p (dst, src1))
  dst = gen_reg_rtx (mode);

/* Source 1 cannot be a constant.  */
if (CONSTANT_P (src1)((rtx_class[(int) (((enum rtx_code) (src1)->code))]) == RTX_CONST_OBJ
))
  src1 = force_reg (mode, src1);

/* Source 1 cannot be a non-matching memory.  */
if (MEM_P (src1)(((enum rtx_code) (src1)->code) == MEM) && !rtx_equal_p (dst, src1))
  src1 = force_reg (mode, src1);

/* Improve address combine.  */
if (code == PLUS
    && GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) == MODE_INT
    && MEM_P (src2)(((enum rtx_code) (src2)->code) == MEM))
  src2 = force_reg (mode, src2);

operands[1] = src1;
operands[2] = src2;
return dst;
920}

922/* Similarly, but assume that the destination has already been
 set up properly.  */

925void
926ix86_fixup_binary_operands_no_copy (enum rtx_code code,
		    machine_mode mode, rtx operands[])
928{
rtx dst = ix86_fixup_binary_operands (code, mode, operands);
gcc_assert (dst == operands[0])((void)(!(dst == operands[0]) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 930, __FUNCTION__), 0 : 0));
931}

933/* Attempt to expand a binary operator.  Make the expansion closer to the
 actual machine, then just general_operand, which will allow 3 separate
 memory references (one output, two input) in a single insn.  */

937void
938ix86_expand_binary_operator (enum rtx_code code, machine_mode mode,
	     rtx operands[])
940{
rtx src1, src2, dst, op, clob;

dst = ix86_fixup_binary_operands (code, mode, operands);
src1 = operands[1];
src2 = operands[2];

/* Emit the instruction.  */

op = gen_rtx_SET (dst, gen_rtx_fmt_ee (code, mode, src1, src2))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dst))
, ((gen_rtx_fmt_ee_stat ((code), (mode), (src1), (src2) ))) );

if (reload_completed
    && code == PLUS
    && !rtx_equal_p (dst, src1))
  {
    /* This is going to be an LEA; avoid splitting it later.  */
    emit_insn (op);
  }
else
  {
    clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG))gen_rtx_fmt_e_stat ((CLOBBER), ((((void) 0, E_VOIDmode))), ((
gen_rtx_REG (((void) 0, E_CCmode), 17))) );
    emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, op, clob))) ));
  }

/* Fix up the destination if needed.  */
if (dst != operands[0])
  emit_move_insn (operands[0], dst);
967}

969/* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
 the given OPERANDS.  */

972void
973ix86_expand_vector_logical_operator (enum rtx_code code, machine_mode mode,
		     rtx operands[])
975{
rtx op1 = NULL_RTX(rtx) 0, op2 = NULL_RTX(rtx) 0;
if (SUBREG_P (operands[1])(((enum rtx_code) (operands[1])->code) == SUBREG))
  {
    op1 = operands[1];
    op2 = operands[2];
  }
else if (SUBREG_P (operands[2])(((enum rtx_code) (operands[2])->code) == SUBREG))
  {
    op1 = operands[2];
    op2 = operands[1];
  }
/* Optimize (__m128i) d | (__m128i) e and similar code
   when d and e are float vectors into float vector logical
   insn.  In C/C++ without using intrinsics there is no other way
   to express vector logical operation on float vectors than
   to cast them temporarily to integer vectors.  */
if (op1
    && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMALix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL]
    && (SUBREG_P (op2)(((enum rtx_code) (op2)->code) == SUBREG) || GET_CODE (op2)((enum rtx_code) (op2)->code) == CONST_VECTOR)
    && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op1)))((enum mode_class) mode_class[((machine_mode) ((((op1)->u.
fld[0]).rt_rtx))->mode)]) == MODE_VECTOR_FLOAT
    && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op1)))((unsigned short) mode_to_bytes (((machine_mode) ((((op1)->
u.fld[0]).rt_rtx))->mode)).coeffs[0]) == GET_MODE_SIZE (mode)((unsigned short) mode_to_bytes (mode).coeffs[0])
    && SUBREG_BYTE (op1)(((op1)->u.fld[1]).rt_subreg) == 0
    && (GET_CODE (op2)((enum rtx_code) (op2)->code) == CONST_VECTOR
 || (GET_MODE (SUBREG_REG (op1))((machine_mode) ((((op1)->u.fld[0]).rt_rtx))->mode) == GET_MODE (SUBREG_REG (op2))((machine_mode) ((((op2)->u.fld[0]).rt_rtx))->mode)
     && SUBREG_BYTE (op2)(((op2)->u.fld[1]).rt_subreg) == 0))
    && can_create_pseudo_p ()(!reload_in_progress && !reload_completed))
  {
    rtx dst;
    switch (GET_MODE (SUBREG_REG (op1))((machine_mode) ((((op1)->u.fld[0]).rt_rtx))->mode))
{
case E_V4SFmode:
case E_V8SFmode:
case E_V16SFmode:
case E_V2DFmode:
case E_V4DFmode:
case E_V8DFmode:
 dst = gen_reg_rtx (GET_MODE (SUBREG_REG (op1))((machine_mode) ((((op1)->u.fld[0]).rt_rtx))->mode));
 if (GET_CODE (op2)((enum rtx_code) (op2)->code) == CONST_VECTOR)
   {
     op2 = gen_lowpartrtl_hooks.gen_lowpart (GET_MODE (dst)((machine_mode) (dst)->mode), op2);
     op2 = force_reg (GET_MODE (dst)((machine_mode) (dst)->mode), op2);
   }
 else
   {
     op1 = operands[1];
     op2 = SUBREG_REG (operands[2])(((operands[2])->u.fld[0]).rt_rtx);
     if (!vector_operand (op2, GET_MODE (dst)((machine_mode) (dst)->mode)))
op2 = force_reg (GET_MODE (dst)((machine_mode) (dst)->mode), op2);
   }
 op1 = SUBREG_REG (op1)(((op1)->u.fld[0]).rt_rtx);
 if (!vector_operand (op1, GET_MODE (dst)((machine_mode) (dst)->mode)))
   op1 = force_reg (GET_MODE (dst)((machine_mode) (dst)->mode), op1);
 emit_insn (gen_rtx_SET (dst,gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dst))
, ((gen_rtx_fmt_ee_stat ((code), (((machine_mode) (dst)->mode
)), (op1), (op2) ))) )
		  gen_rtx_fmt_ee (code, GET_MODE (dst),gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dst))
, ((gen_rtx_fmt_ee_stat ((code), (((machine_mode) (dst)->mode
)), (op1), (op2) ))) )
				  op1, op2))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dst))
, ((gen_rtx_fmt_ee_stat ((code), (((machine_mode) (dst)->mode
)), (op1), (op2) ))) ));
 emit_move_insn (operands[0], gen_lowpartrtl_hooks.gen_lowpart (mode, dst));
 return;
default:
 break;
}
  }
if (!vector_operand (operands[1], mode))
  operands[1] = force_reg (mode, operands[1]);
if (!vector_operand (operands[2], mode))
  operands[2] = force_reg (mode, operands[2]);
ix86_fixup_binary_operands_no_copy (code, mode, operands);
emit_insn (gen_rtx_SET (operands[0],gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((operands
[0])), ((gen_rtx_fmt_ee_stat ((code), (mode), (operands[1]), (
operands[2]) ))) )
	  gen_rtx_fmt_ee (code, mode, operands[1],gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((operands
[0])), ((gen_rtx_fmt_ee_stat ((code), (mode), (operands[1]), (
operands[2]) ))) )
			  operands[2]))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((operands
[0])), ((gen_rtx_fmt_ee_stat ((code), (mode), (operands[1]), (
operands[2]) ))) ));
1045}

1047/* Return TRUE or FALSE depending on whether the binary operator meets the
 appropriate constraints.  */

1050bool
1051ix86_binary_operator_ok (enum rtx_code code, machine_mode mode,
	 rtx operands[3])
1053{
rtx dst = operands[0];
rtx src1 = operands[1];
rtx src2 = operands[2];

/* Both source operands cannot be in memory.  */
if ((MEM_P (src1)(((enum rtx_code) (src1)->code) == MEM) || bcst_mem_operand (src1, mode))
    && (MEM_P (src2)(((enum rtx_code) (src2)->code) == MEM) || bcst_mem_operand (src2, mode)))
  return false;

/* Canonicalize operand order for commutative operators.  */
if (ix86_swap_binary_operands_p (code, mode, operands))
  std::swap (src1, src2);

/* If the destination is memory, we must have a matching source operand.  */
if (MEM_P (dst)(((enum rtx_code) (dst)->code) == MEM) && !rtx_equal_p (dst, src1))
  return false;

/* Source 1 cannot be a constant.  */
if (CONSTANT_P (src1)((rtx_class[(int) (((enum rtx_code) (src1)->code))]) == RTX_CONST_OBJ
))
  return false;

/* Source 1 cannot be a non-matching memory.  */
if (MEM_P (src1)(((enum rtx_code) (src1)->code) == MEM) && !rtx_equal_p (dst, src1))
  /* Support "andhi/andsi/anddi" as a zero-extending move.  */
  return (code == AND
   && (mode == HImode(scalar_int_mode ((scalar_int_mode::from_int) E_HImode))
|| mode == SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode))
|| (TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
) && mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode))))
   && satisfies_constraint_L (src2));

return true;
1085}

1087/* Attempt to expand a unary operator.  Make the expansion closer to the
 actual machine, then just general_operand, which will allow 2 separate
 memory references (one output, one input) in a single insn.  */

1091void
1092ix86_expand_unary_operator (enum rtx_code code, machine_mode mode,
	    rtx operands[])
1094{
bool matching_memory = false;
rtx src, dst, op, clob;

dst = operands[0];
src = operands[1];

/* If the destination is memory, and we do not have matching source
   operands, do things in registers.  */
if (MEM_P (dst)(((enum rtx_code) (dst)->code) == MEM))
  {
    if (rtx_equal_p (dst, src))
matching_memory = true;
    else
dst = gen_reg_rtx (mode);
  }

/* When source operand is memory, destination must match.  */
if (MEM_P (src)(((enum rtx_code) (src)->code) == MEM) && !matching_memory)
  src = force_reg (mode, src);

/* Emit the instruction.  */

op = gen_rtx_SET (dst, gen_rtx_fmt_e (code, mode, src))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dst))
, ((gen_rtx_fmt_e_stat ((code), (mode), (src) ))) );

if (code == NOT)
  emit_insn (op);
else
  {
    clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG))gen_rtx_fmt_e_stat ((CLOBBER), ((((void) 0, E_VOIDmode))), ((
gen_rtx_REG (((void) 0, E_CCmode), 17))) );
    emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, op, clob))) ));
  }

/* Fix up the destination if needed.  */
if (dst != operands[0])
  emit_move_insn (operands[0], dst);
1130}

1132/* Predict just emitted jump instruction to be taken with probability PROB.  */

1134static void
1135predict_jump (int prob)
1136{
rtx_insn *insn = get_last_insn ();
gcc_assert (JUMP_P (insn))((void)(!((((enum rtx_code) (insn)->code) == JUMP_INSN)) ?
 fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 1138, __FUNCTION__), 0 : 0));
add_reg_br_prob_note (insn, profile_probability::from_reg_br_prob_base (prob));
1140}

1142/* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
 divisor are within the range [0-255].  */

1145void
1146ix86_split_idivmod (machine_mode mode, rtx operands[],
    bool unsigned_p)
1148{
rtx_code_label *end_label, *qimode_label;
rtx div, mod;
rtx_insn *insn;
rtx scratch, tmp0, tmp1, tmp2;
rtx (*gen_divmod4_1) (rtx, rtx, rtx, rtx);

switch (mode)
  {
  case E_SImode:
    if (GET_MODE (operands[0])((machine_mode) (operands[0])->mode) == SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)))
{
 if (GET_MODE (operands[1])((machine_mode) (operands[1])->mode) == SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)))
   gen_divmod4_1 = unsigned_p ? gen_udivmodsi4_1 : gen_divmodsi4_1;
 else
   gen_divmod4_1
     = unsigned_p ? gen_udivmodsi4_zext_2 : gen_divmodsi4_zext_2;
}
    else
gen_divmod4_1
 = unsigned_p ? gen_udivmodsi4_zext_1 : gen_divmodsi4_zext_1;
    break;

  case E_DImode:
    gen_divmod4_1 = unsigned_p ? gen_udivmoddi4_1 : gen_divmoddi4_1;
    break;

  default:
    gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 1176, __FUNCTION__));
  }

end_label = gen_label_rtx ();
qimode_label = gen_label_rtx ();

scratch = gen_reg_rtx (mode);

/* Use 8bit unsigned divimod if dividend and divisor are within
   the range [0-255].  */
emit_move_insn (scratch, operands[2]);
scratch = expand_simple_binop (mode, IOR, scratch, operands[3],
		 scratch, 1, OPTAB_DIRECT);
emit_insn (gen_test_ccno_1 (mode, scratch, GEN_INT (-0x100)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (-0x100))));
tmp0 = gen_rtx_REG (CCNOmode((void) 0, E_CCNOmode), FLAGS_REG17);
tmp0 = gen_rtx_EQ (VOIDmode, tmp0, const0_rtx)gen_rtx_fmt_ee_stat ((EQ), ((((void) 0, E_VOIDmode))), ((tmp0
)), (((const_int_rtx[64]))) );
tmp0 = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp0,gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((((void) 0, E_VOIDmode
))), ((tmp0)), ((gen_rtx_fmt_u_stat ((LABEL_REF), ((((void) 0
, E_VOIDmode))), ((qimode_label)) ))), ((pc_rtx)) )
	       gen_rtx_LABEL_REF (VOIDmode, qimode_label),gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((((void) 0, E_VOIDmode
))), ((tmp0)), ((gen_rtx_fmt_u_stat ((LABEL_REF), ((((void) 0
, E_VOIDmode))), ((qimode_label)) ))), ((pc_rtx)) )
	       pc_rtx)gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((((void) 0, E_VOIDmode
))), ((tmp0)), ((gen_rtx_fmt_u_stat ((LABEL_REF), ((((void) 0
, E_VOIDmode))), ((qimode_label)) ))), ((pc_rtx)) );
insn = emit_jump_insn (gen_rtx_SET (pc_rtx, tmp0)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((pc_rtx
)), ((tmp0)) ));
predict_jump (REG_BR_PROB_BASE10000 * 50 / 100);
JUMP_LABEL (insn)(((insn)->u.fld[7]).rt_rtx) = qimode_label;

/* Generate original signed/unsigned divimod.  */
emit_insn (gen_divmod4_1 (operands[0], operands[1],
	    operands[2], operands[3]));

/* Branch to the end.  */
emit_jump_insn (gen_jump (end_label));
emit_barrier ();

/* Generate 8bit unsigned divide.  */
emit_label (qimode_label);
/* Don't use operands[0] for result of 8bit divide since not all
   registers support QImode ZERO_EXTRACT.  */
tmp0 = lowpart_subreg (HImode(scalar_int_mode ((scalar_int_mode::from_int) E_HImode)), scratch, mode);
tmp1 = lowpart_subreg (HImode(scalar_int_mode ((scalar_int_mode::from_int) E_HImode)), operands[2], mode);
tmp2 = lowpart_subreg (QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)), operands[3], mode);
emit_insn (gen_udivmodhiqi3 (tmp0, tmp1, tmp2));

if (unsigned_p)
  {
    div = gen_rtx_UDIV (mode, operands[2], operands[3])gen_rtx_fmt_ee_stat ((UDIV), ((mode)), ((operands[2])), ((operands
[3])) );
    mod = gen_rtx_UMOD (mode, operands[2], operands[3])gen_rtx_fmt_ee_stat ((UMOD), ((mode)), ((operands[2])), ((operands
[3])) );
  }
else
  {
    div = gen_rtx_DIV (mode, operands[2], operands[3])gen_rtx_fmt_ee_stat ((DIV), ((mode)), ((operands[2])), ((operands
[3])) );
    mod = gen_rtx_MOD (mode, operands[2], operands[3])gen_rtx_fmt_ee_stat ((MOD), ((mode)), ((operands[2])), ((operands
[3])) );
  }
if (mode == SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)))
  {
    if (GET_MODE (operands[0])((machine_mode) (operands[0])->mode) != SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)))
div = gen_rtx_ZERO_EXTEND (DImode, div)gen_rtx_fmt_e_stat ((ZERO_EXTEND), (((scalar_int_mode ((scalar_int_mode
::from_int) E_DImode)))), ((div)) );
    if (GET_MODE (operands[1])((machine_mode) (operands[1])->mode) != SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)))
mod = gen_rtx_ZERO_EXTEND (DImode, mod)gen_rtx_fmt_e_stat ((ZERO_EXTEND), (((scalar_int_mode ((scalar_int_mode
::from_int) E_DImode)))), ((mod)) );
  }

/* Extract remainder from AH.  */
scratch = gen_lowpartrtl_hooks.gen_lowpart (GET_MODE (operands[1])((machine_mode) (operands[1])->mode), scratch);
tmp1 = gen_rtx_ZERO_EXTRACT (GET_MODE (operands[1]), scratch,gen_rtx_fmt_eee_stat ((ZERO_EXTRACT), ((((machine_mode) (operands
[1])->mode))), ((scratch)), ((gen_rtx_CONST_INT (((void) 0
, E_VOIDmode), (8)))), ((gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (8)))) )
	       GEN_INT (8), GEN_INT (8))gen_rtx_fmt_eee_stat ((ZERO_EXTRACT), ((((machine_mode) (operands
[1])->mode))), ((scratch)), ((gen_rtx_CONST_INT (((void) 0
, E_VOIDmode), (8)))), ((gen_rtx_CONST_INT (((void) 0, E_VOIDmode
), (8)))) );
insn = emit_move_insn (operands[1], tmp1);
set_unique_reg_note (insn, REG_EQUAL, mod);

/* Zero extend quotient from AL.  */
tmp1 = gen_lowpartrtl_hooks.gen_lowpart (QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)), tmp0);
insn = emit_insn (gen_extend_insn
    (operands[0], tmp1,
     GET_MODE (operands[0])((machine_mode) (operands[0])->mode), QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)), 1));
set_unique_reg_note (insn, REG_EQUAL, div);

emit_label (end_label);
1249}

1251/* Emit x86 binary operand CODE in mode MODE, where the first operand
 matches destination.  RTX includes clobber of FLAGS_REG.  */

1254void
1255ix86_emit_binop (enum rtx_code code, machine_mode mode,
 rtx dst, rtx src)
1257{
rtx op, clob;

op = gen_rtx_SET (dst, gen_rtx_fmt_ee (code, mode, dst, src))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dst))
, ((gen_rtx_fmt_ee_stat ((code), (mode), (dst), (src) ))) );
clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG))gen_rtx_fmt_e_stat ((CLOBBER), ((((void) 0, E_VOIDmode))), ((
gen_rtx_REG (((void) 0, E_CCmode), 17))) );

emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(gen_rtvec (2, op, clob))) ));
1264}

1266/* Return true if regno1 def is nearest to the insn.  */

1268static bool
1269find_nearest_reg_def (rtx_insn *insn, int regno1, int regno2)
1270{
rtx_insn *prev = insn;
rtx_insn *start = BB_HEAD (BLOCK_FOR_INSN (insn))(BLOCK_FOR_INSN (insn))->il.x.head_;

if (insn == start)
  return false;
while (prev && prev != start)
  {
    if (!INSN_P (prev)(((((enum rtx_code) (prev)->code) == INSN) || (((enum rtx_code
) (prev)->code) == JUMP_INSN) || (((enum rtx_code) (prev)->
code) == CALL_INSN)) || (((enum rtx_code) (prev)->code) ==
 DEBUG_INSN)) || !NONDEBUG_INSN_P (prev)((((enum rtx_code) (prev)->code) == INSN) || (((enum rtx_code
) (prev)->code) == JUMP_INSN) || (((enum rtx_code) (prev)->
code) == CALL_INSN)))
{
 prev = PREV_INSN (prev);
 continue;
}
    if (insn_defines_reg (regno1, INVALID_REGNUM(~(unsigned int) 0), prev))
return true;
    else if (insn_defines_reg (regno2, INVALID_REGNUM(~(unsigned int) 0), prev))
return false;
    prev = PREV_INSN (prev);
  }

/* None of the regs is defined in the bb.  */
return false;
1292}

1294/* Split lea instructions into a sequence of instructions
 which are executed on ALU to avoid AGU stalls.
 It is assumed that it is allowed to clobber flags register
 at lea position.  */

1299void
1300ix86_split_lea_for_addr (rtx_insn *insn, rtx operands[], machine_mode mode)
1301{
unsigned int regno0, regno1, regno2;
struct ix86_address parts;
rtx target, tmp;
int ok, adds;

ok = ix86_decompose_address (operands[1], &parts);
gcc_assert (ok)((void)(!(ok) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 1308, __FUNCTION__), 0 : 0));

target = gen_lowpartrtl_hooks.gen_lowpart (mode, operands[0]);

regno0 = true_regnum (target);
regno1 = INVALID_REGNUM(~(unsigned int) 0);
regno2 = INVALID_REGNUM(~(unsigned int) 0);

if (parts.base)
  {
    parts.base = gen_lowpartrtl_hooks.gen_lowpart (mode, parts.base);
    regno1 = true_regnum (parts.base);
  }

if (parts.index)
  {
    parts.index = gen_lowpartrtl_hooks.gen_lowpart (mode, parts.index);
    regno2 = true_regnum (parts.index);
  }

if (parts.disp)
  parts.disp = gen_lowpartrtl_hooks.gen_lowpart (mode, parts.disp);

if (parts.scale > 1)
  {
    /* Case r1 = r1 + ...  */
    if (regno1 == regno0)
{
 /* If we have a case r1 = r1 + C * r2 then we
    should use multiplication which is very
    expensive.  Assume cost model is wrong if we
    have such case here.  */
 gcc_assert (regno2 != regno0)((void)(!(regno2 != regno0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 1340, __FUNCTION__), 0 : 0));

 for (adds = parts.scale; adds > 0; adds--)
   ix86_emit_binop (PLUS, mode, target, parts.index);
}
    else
{
 /* r1 = r2 + r3 * C case.  Need to move r3 into r1.  */
 if (regno0 != regno2)
   emit_insn (gen_rtx_SET (target, parts.index)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((target
)), ((parts.index)) ));

 /* Use shift for scaling.  */
 ix86_emit_binop (ASHIFT, mode, target,
	   GEN_INT (exact_log2 (parts.scale))gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (exact_log2 (parts
.scale))));

 if (parts.base)
   ix86_emit_binop (PLUS, mode, target, parts.base);

 if (parts.disp && parts.disp != const0_rtx(const_int_rtx[64]))
   ix86_emit_binop (PLUS, mode, target, parts.disp);
}
  }
else if (!parts.base && !parts.index)
  {
    gcc_assert(parts.disp)((void)(!(parts.disp) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 1364, __FUNCTION__), 0 : 0));
    emit_insn (gen_rtx_SET (target, parts.disp)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((target
)), ((parts.disp)) ));
  }
else
  {
    if (!parts.base)
{
 if (regno0 != regno2)
   emit_insn (gen_rtx_SET (target, parts.index)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((target
)), ((parts.index)) ));
}
    else if (!parts.index)
{
 if (regno0 != regno1)
   emit_insn (gen_rtx_SET (target, parts.base)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((target
)), ((parts.base)) ));
}
    else
{
 if (regno0 == regno1)
   tmp = parts.index;
 else if (regno0 == regno2)
   tmp = parts.base;
 else
   {
     rtx tmp1;

     /* Find better operand for SET instruction, depending
 on which definition is farther from the insn.  */
     if (find_nearest_reg_def (insn, regno1, regno2))
tmp = parts.index, tmp1 = parts.base;
     else
tmp = parts.base, tmp1 = parts.index;

     emit_insn (gen_rtx_SET (target, tmp)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((target
)), ((tmp)) ));

     if (parts.disp && parts.disp != const0_rtx(const_int_rtx[64]))
ix86_emit_binop (PLUS, mode, target, parts.disp);

     ix86_emit_binop (PLUS, mode, target, tmp1);
     return;
   }

 ix86_emit_binop (PLUS, mode, target, tmp);
}

    if (parts.disp && parts.disp != const0_rtx(const_int_rtx[64]))
ix86_emit_binop (PLUS, mode, target, parts.disp);
  }
1411}

1413/* Post-reload splitter for converting an SF or DFmode value in an
 SSE register into an unsigned SImode.  */

1416void
1417ix86_split_convert_uns_si_sse (rtx operands[])
1418{
machine_mode vecmode;
rtx value, large, zero_or_two31, input, two31, x;

large = operands[1];
zero_or_two31 = operands[2];
input = operands[3];
two31 = operands[4];
vecmode = GET_MODE (large)((machine_mode) (large)->mode);
value = gen_rtx_REG (vecmode, REGNO (operands[0])(rhs_regno(operands[0])));

/* Load up the value into the low element.  We must ensure that the other
   elements are valid floats -- zero is the easiest such value.  */
if (MEM_P (input)(((enum rtx_code) (input)->code) == MEM))
  {
    if (vecmode == V4SFmode((void) 0, E_V4SFmode))
emit_insn (gen_vec_setv4sf_0 (value, CONST0_RTX (V4SFmode)(const_tiny_rtx[0][(int) (((void) 0, E_V4SFmode))]), input));
    else
emit_insn (gen_sse2_loadlpd (value, CONST0_RTX (V2DFmode)(const_tiny_rtx[0][(int) (((void) 0, E_V2DFmode))]), input));
  }
else
  {
    input = gen_rtx_REG (vecmode, REGNO (input)(rhs_regno(input)));
    emit_move_insn (value, CONST0_RTX (vecmode)(const_tiny_rtx[0][(int) (vecmode)]));
    if (vecmode == V4SFmode((void) 0, E_V4SFmode))
emit_insn (gen_sse_movss (value, value, input));
    else
emit_insn (gen_sse2_movsd (value, value, input));
  }

emit_move_insn (large, two31);
emit_move_insn (zero_or_two31, MEM_P (two31)(((enum rtx_code) (two31)->code) == MEM) ? large : two31);

x = gen_rtx_fmt_ee (LE, vecmode, large, value)gen_rtx_fmt_ee_stat ((LE), (vecmode), (large), (value) );
emit_insn (gen_rtx_SET (large, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((large
)), ((x)) ));

x = gen_rtx_AND (vecmode, zero_or_two31, large)gen_rtx_fmt_ee_stat ((AND), ((vecmode)), ((zero_or_two31)), (
(large)) );
emit_insn (gen_rtx_SET (zero_or_two31, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((zero_or_two31
)), ((x)) ));

x = gen_rtx_MINUS (vecmode, value, zero_or_two31)gen_rtx_fmt_ee_stat ((MINUS), ((vecmode)), ((value)), ((zero_or_two31
)) );
emit_insn (gen_rtx_SET (value, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((value
)), ((x)) ));

large = gen_rtx_REG (V4SImode((void) 0, E_V4SImode), REGNO (large)(rhs_regno(large)));
emit_insn (gen_ashlv4si3 (large, large, GEN_INT (31)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (31))));

x = gen_rtx_REG (V4SImode((void) 0, E_V4SImode), REGNO (value)(rhs_regno(value)));
if (vecmode == V4SFmode((void) 0, E_V4SFmode))
  emit_insn (gen_fix_truncv4sfv4si2 (x, value));
else
  emit_insn (gen_sse2_cvttpd2dq (x, value));
value = x;

emit_insn (gen_xorv4si3 (value, value, large));
1471}

1473static bool ix86_expand_vector_init_one_nonzero (bool mmx_ok,
				 machine_mode mode, rtx target,
				 rtx var, int one_var);

1477/* Convert an unsigned DImode value into a DFmode, using only SSE.
 Expects the 64-bit DImode to be supplied in a pair of integral
 registers.  Requires SSE2; will use SSE3 if available.  For x86_32,
 -mfpmath=sse, !optimize_size only.  */

1482void
1483ix86_expand_convert_uns_didf_sse (rtx target, rtx input)
1484{
REAL_VALUE_TYPEstruct real_value bias_lo_rvt, bias_hi_rvt;
rtx int_xmm, fp_xmm;
rtx biases, exponents;
rtx x;

int_xmm = gen_reg_rtx (V4SImode((void) 0, E_V4SImode));
if (TARGET_INTER_UNIT_MOVES_TO_VECix86_tune_features[X86_TUNE_INTER_UNIT_MOVES_TO_VEC])
  emit_insn (gen_movdi_to_sse (int_xmm, input));
else if (TARGET_SSE_SPLIT_REGSix86_tune_features[X86_TUNE_SSE_SPLIT_REGS])
  {
    emit_clobber (int_xmm);
    emit_move_insn (gen_lowpartrtl_hooks.gen_lowpart (DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)), int_xmm), input);
  }
else
  {
    x = gen_reg_rtx (V2DImode((void) 0, E_V2DImode));
    ix86_expand_vector_init_one_nonzero (false, V2DImode((void) 0, E_V2DImode), x, input, 0);
    emit_move_insn (int_xmm, gen_lowpartrtl_hooks.gen_lowpart (V4SImode((void) 0, E_V4SImode), x));
  }

x = gen_rtx_CONST_VECTOR (V4SImode((void) 0, E_V4SImode),
	    gen_rtvec (4, GEN_INT (0x43300000UL)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x43300000UL)),
		       GEN_INT (0x45300000UL)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x45300000UL)),
		       const0_rtx(const_int_rtx[64]), const0_rtx(const_int_rtx[64])));
exponents = validize_mem (force_const_mem (V4SImode((void) 0, E_V4SImode), x));

/* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
emit_insn (gen_vec_interleave_lowv4si (int_xmm, int_xmm, exponents));

/* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
   yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
   Similarly (0x45300000UL ## fp_value_hi_xmm) yields
   (0x1.0p84 + double(fp_value_hi_xmm)).
   Note these exponents differ by 32.  */

fp_xmm = copy_to_mode_reg (V2DFmode((void) 0, E_V2DFmode), gen_lowpartrtl_hooks.gen_lowpart (V2DFmode((void) 0, E_V2DFmode), int_xmm));

/* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
   in [0,2**32-1] and [0]+[2**32,2**64-1] respectively.  */
real_ldexp (&bias_lo_rvt, &dconst1, 52);
real_ldexp (&bias_hi_rvt, &dconst1, 84);
biases = const_double_from_real_value (bias_lo_rvt, DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)));
x = const_double_from_real_value (bias_hi_rvt, DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)));
biases = gen_rtx_CONST_VECTOR (V2DFmode((void) 0, E_V2DFmode), gen_rtvec (2, biases, x));
biases = validize_mem (force_const_mem (V2DFmode((void) 0, E_V2DFmode), biases));
emit_insn (gen_subv2df3 (fp_xmm, fp_xmm, biases));

/* Add the upper and lower DFmode values together.  */
if (TARGET_SSE3((global_options.x_ix86_isa_flags & (1UL << 52)) !=
 0))
  emit_insn (gen_sse3_haddv2df3 (fp_xmm, fp_xmm, fp_xmm));
else
  {
    x = copy_to_mode_reg (V2DFmode((void) 0, E_V2DFmode), fp_xmm);
    emit_insn (gen_vec_interleave_highv2df (fp_xmm, fp_xmm, fp_xmm));
    emit_insn (gen_addv2df3 (fp_xmm, fp_xmm, x));
  }

ix86_expand_vector_extract (false, target, fp_xmm, 0);
1543}

1545/* Not used, but eases macroization of patterns.  */
1546void
1547ix86_expand_convert_uns_sixf_sse (rtx, rtx)
1548{
gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 1549, __FUNCTION__));
1550}

1552/* Convert an unsigned SImode value into a DFmode.  Only currently used
 for SSE, but applicable anywhere.  */

1555void
1556ix86_expand_convert_uns_sidf_sse (rtx target, rtx input)
1557{
REAL_VALUE_TYPEstruct real_value TWO31r;
rtx x, fp;

x = expand_simple_binop (SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), PLUS, input, GEN_INT (-2147483647 - 1)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (-2147483647 - 1)),
	   NULL__null, 1, OPTAB_DIRECT);

fp = gen_reg_rtx (DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)));
emit_insn (gen_floatsidf2 (fp, x));

real_ldexp (&TWO31r, &dconst1, 31);
x = const_double_from_real_value (TWO31r, DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)));

x = expand_simple_binop (DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)), PLUS, fp, x, target, 0, OPTAB_DIRECT);
if (x != target)
  emit_move_insn (target, x);
1573}

1575/* Convert a signed DImode value into a DFmode.  Only used for SSE in
 32-bit mode; otherwise we have a direct convert instruction.  */

1578void
1579ix86_expand_convert_sign_didf_sse (rtx target, rtx input)
1580{
REAL_VALUE_TYPEstruct real_value TWO32r;
rtx fp_lo, fp_hi, x;

fp_lo = gen_reg_rtx (DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)));
fp_hi = gen_reg_rtx (DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)));

emit_insn (gen_floatsidf2 (fp_hi, gen_highpart (SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), input)));

real_ldexp (&TWO32r, &dconst1, 32);
x = const_double_from_real_value (TWO32r, DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)));
fp_hi = expand_simple_binop (DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)), MULT, fp_hi, x, fp_hi, 0, OPTAB_DIRECT);

ix86_expand_convert_uns_sidf_sse (fp_lo, gen_lowpartrtl_hooks.gen_lowpart (SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), input));

x = expand_simple_binop (DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)), PLUS, fp_hi, fp_lo, target,
	   0, OPTAB_DIRECT);
if (x != target)
  emit_move_insn (target, x);
1599}

1601/* Convert an unsigned SImode value into a SFmode, using only SSE.
 For x86_32, -mfpmath=sse, !optimize_size only.  */
1603void
1604ix86_expand_convert_uns_sisf_sse (rtx target, rtx input)
1605{
REAL_VALUE_TYPEstruct real_value ONE16r;
rtx fp_hi, fp_lo, int_hi, int_lo, x;

real_ldexp (&ONE16r, &dconst1, 16);
x = const_double_from_real_value (ONE16r, SFmode(scalar_float_mode ((scalar_float_mode::from_int) E_SFmode)));
int_lo = expand_simple_binop (SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), AND, input, GEN_INT(0xffff)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0xffff)),
		      NULL__null, 0, OPTAB_DIRECT);
int_hi = expand_simple_binop (SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), LSHIFTRT, input, GEN_INT(16)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (16)),
		      NULL__null, 0, OPTAB_DIRECT);
fp_hi = gen_reg_rtx (SFmode(scalar_float_mode ((scalar_float_mode::from_int) E_SFmode)));
fp_lo = gen_reg_rtx (SFmode(scalar_float_mode ((scalar_float_mode::from_int) E_SFmode)));
emit_insn (gen_floatsisf2 (fp_hi, int_hi));
emit_insn (gen_floatsisf2 (fp_lo, int_lo));
fp_hi = expand_simple_binop (SFmode(scalar_float_mode ((scalar_float_mode::from_int) E_SFmode)), MULT, fp_hi, x, fp_hi,
	       0, OPTAB_DIRECT);
fp_hi = expand_simple_binop (SFmode(scalar_float_mode ((scalar_float_mode::from_int) E_SFmode)), PLUS, fp_hi, fp_lo, target,
	       0, OPTAB_DIRECT);
if (!rtx_equal_p (target, fp_hi))
  emit_move_insn (target, fp_hi);
1625}

1627/* floatunsv{4,8}siv{4,8}sf2 expander.  Expand code to convert
 a vector of unsigned ints VAL to vector of floats TARGET.  */

1630void
1631ix86_expand_vector_convert_uns_vsivsf (rtx target, rtx val)
1632{
rtx tmp[8];
REAL_VALUE_TYPEstruct real_value TWO16r;
machine_mode intmode = GET_MODE (val)((machine_mode) (val)->mode);
machine_mode fltmode = GET_MODE (target)((machine_mode) (target)->mode);
rtx (*cvt) (rtx, rtx);

if (intmode == V4SImode((void) 0, E_V4SImode))
  cvt = gen_floatv4siv4sf2;
else
  cvt = gen_floatv8siv8sf2;
tmp[0] = ix86_build_const_vector (intmode, 1, GEN_INT (0xffff)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0xffff)));
tmp[0] = force_reg (intmode, tmp[0]);
tmp[1] = expand_simple_binop (intmode, AND, val, tmp[0], NULL_RTX(rtx) 0, 1,
		OPTAB_DIRECT);
tmp[2] = expand_simple_binop (intmode, LSHIFTRT, val, GEN_INT (16)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (16)),
		NULL_RTX(rtx) 0, 1, OPTAB_DIRECT);
tmp[3] = gen_reg_rtx (fltmode);
emit_insn (cvt (tmp[3], tmp[1]));
tmp[4] = gen_reg_rtx (fltmode);
emit_insn (cvt (tmp[4], tmp[2]));
real_ldexp (&TWO16r, &dconst1, 16);
tmp[5] = const_double_from_real_value (TWO16r, SFmode(scalar_float_mode ((scalar_float_mode::from_int) E_SFmode)));
tmp[5] = force_reg (fltmode, ix86_build_const_vector (fltmode, 1, tmp[5]));
tmp[6] = expand_simple_binop (fltmode, MULT, tmp[4], tmp[5], NULL_RTX(rtx) 0, 1,
		OPTAB_DIRECT);
tmp[7] = expand_simple_binop (fltmode, PLUS, tmp[3], tmp[6], target, 1,
		OPTAB_DIRECT);
if (tmp[7] != target)
  emit_move_insn (target, tmp[7]);
1662}

1664/* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
 This is done by doing just signed conversion if < 0x1p31, and otherwise by
 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards.  */

1669rtx
1670ix86_expand_adjust_ufix_to_sfix_si (rtx val, rtx *xorp)
1671{
REAL_VALUE_TYPEstruct real_value TWO31r;
rtx two31r, tmp[4];
machine_mode mode = GET_MODE (val)((machine_mode) (val)->mode);
machine_mode scalarmode = GET_MODE_INNER (mode)(mode_to_inner (mode));
machine_mode intmode = GET_MODE_SIZE (mode)((unsigned short) mode_to_bytes (mode).coeffs[0]) == 32 ? V8SImode((void) 0, E_V8SImode) : V4SImode((void) 0, E_V4SImode);
rtx (*cmp) (rtx, rtx, rtx, rtx);
int i;

for (i = 0; i < 3; i++)
  tmp[i] = gen_reg_rtx (mode);
real_ldexp (&TWO31r, &dconst1, 31);
two31r = const_double_from_real_value (TWO31r, scalarmode);
two31r = ix86_build_const_vector (mode, 1, two31r);
two31r = force_reg (mode, two31r);
switch (mode)
  {
  case E_V8SFmode: cmp = gen_avx_maskcmpv8sf3; break;
  case E_V4SFmode: cmp = gen_sse_maskcmpv4sf3; break;
  case E_V4DFmode: cmp = gen_avx_maskcmpv4df3; break;
  case E_V2DFmode: cmp = gen_sse2_maskcmpv2df3; break;
  default: gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 1692, __FUNCTION__));
  }
tmp[3] = gen_rtx_LE (mode, two31r, val)gen_rtx_fmt_ee_stat ((LE), ((mode)), ((two31r)), ((val)) );
emit_insn (cmp (tmp[0], two31r, val, tmp[3]));
tmp[1] = expand_simple_binop (mode, AND, tmp[0], two31r, tmp[1],
		0, OPTAB_DIRECT);
if (intmode == V4SImode((void) 0, E_V4SImode) || TARGET_AVX2((global_options.x_ix86_isa_flags & (1UL << 9)) != 0
))
  *xorp = expand_simple_binop (intmode, ASHIFT,
		 gen_lowpartrtl_hooks.gen_lowpart (intmode, tmp[0]),
		 GEN_INT (31)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (31)), NULL_RTX(rtx) 0, 0,
		 OPTAB_DIRECT);
else
  {
    rtx two31 = gen_int_mode (HOST_WIDE_INT_1U1UL << 31, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)));
    two31 = ix86_build_const_vector (intmode, 1, two31);
    *xorp = expand_simple_binop (intmode, AND,
		   gen_lowpartrtl_hooks.gen_lowpart (intmode, tmp[0]),
		   two31, NULL_RTX(rtx) 0, 0,
		   OPTAB_DIRECT);
  }
return expand_simple_binop (mode, MINUS, val, tmp[1], tmp[2],
	      0, OPTAB_DIRECT);
1714}

1716/* Generate code for floating point ABS or NEG.  */

1718void
1719ix86_expand_fp_absneg_operator (enum rtx_code code, machine_mode mode,
		rtx operands[])
1721{
rtx set, dst, src;
bool use_sse = false;
bool vector_mode = VECTOR_MODE_P (mode)(((enum mode_class) mode_class[mode]) == MODE_VECTOR_BOOL || (
(enum mode_class) mode_class[mode]) == MODE_VECTOR_INT || ((enum
 mode_class) mode_class[mode]) == MODE_VECTOR_FLOAT || ((enum
 mode_class) mode_class[mode]) == MODE_VECTOR_FRACT || ((enum
 mode_class) mode_class[mode]) == MODE_VECTOR_UFRACT || ((enum
 mode_class) mode_class[mode]) == MODE_VECTOR_ACCUM || ((enum
 mode_class) mode_class[mode]) == MODE_VECTOR_UACCUM);
machine_mode vmode = mode;
rtvec par;

if (vector_mode || mode == TFmode(scalar_float_mode ((scalar_float_mode::from_int) E_TFmode)))
  use_sse = true;
else if (TARGET_SSE_MATH((global_options.x_ix86_fpmath & FPMATH_SSE) != 0))
  {
    use_sse = SSE_FLOAT_MODE_P (mode)((((global_options.x_ix86_isa_flags & (1UL << 50)) !=
 0) && (mode) == (scalar_float_mode ((scalar_float_mode
::from_int) E_SFmode))) || (((global_options.x_ix86_isa_flags
 & (1UL << 51)) != 0) && (mode) == (scalar_float_mode
 ((scalar_float_mode::from_int) E_DFmode))));
    if (mode == SFmode(scalar_float_mode ((scalar_float_mode::from_int) E_SFmode)))
vmode = V4SFmode((void) 0, E_V4SFmode);
    else if (mode == DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)))
vmode = V2DFmode((void) 0, E_V2DFmode);
  }

dst = operands[0];
src = operands[1];

set = gen_rtx_fmt_e (code, mode, src)gen_rtx_fmt_e_stat ((code), (mode), (src) );
set = gen_rtx_SET (dst, set)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dst))
, ((set)) );

if (use_sse)
  {
    rtx mask, use, clob;

    /* NEG and ABS performed with SSE use bitwise mask operations.
Create the appropriate mask now.  */
    mask = ix86_build_signbit_mask (vmode, vector_mode, code == ABS);
    use = gen_rtx_USE (VOIDmode, mask)gen_rtx_fmt_e_stat ((USE), ((((void) 0, E_VOIDmode))), ((mask
)) );
    if (vector_mode || mode == TFmode(scalar_float_mode ((scalar_float_mode::from_int) E_TFmode)))
par = gen_rtvec (2, set, use);
    else
{
        clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG))gen_rtx_fmt_e_stat ((CLOBBER), ((((void) 0, E_VOIDmode))), ((
gen_rtx_REG (((void) 0, E_CCmode), 17))) );
 par = gen_rtvec (3, set, use, clob);
      }
  }
else
  {
    rtx clob;

    /* Changing of sign for FP values is doable using integer unit too.  */
    clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG))gen_rtx_fmt_e_stat ((CLOBBER), ((((void) 0, E_VOIDmode))), ((
gen_rtx_REG (((void) 0, E_CCmode), 17))) );
    par = gen_rtvec (2, set, clob);
  }

emit_insn (gen_rtx_PARALLEL (VOIDmode, par)gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(par)) ));
1771}

1773/* Deconstruct a floating point ABS or NEG operation
 with integer registers into integer operations.  */

1776void
1777ix86_split_fp_absneg_operator (enum rtx_code code, machine_mode mode,
	       rtx operands[])
1779{
enum rtx_code absneg_op;
rtx dst, set;

gcc_assert (operands_match_p (operands[0], operands[1]))((void)(!(operands_match_p (operands[0], operands[1])) ? fancy_abort
 ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 1783, __FUNCTION__), 0 : 0));

switch (mode)
  {
  case E_SFmode:
    dst = gen_lowpartrtl_hooks.gen_lowpart (SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), operands[0]);

    if (code == ABS)
{
 set = gen_int_mode (0x7fffffff, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)));
 absneg_op = AND;
}
    else
{
 set = gen_int_mode (0x80000000, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)));
 absneg_op = XOR;
}
    set = gen_rtx_fmt_ee (absneg_op, SImode, dst, set)gen_rtx_fmt_ee_stat ((absneg_op), ((scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), (dst), (set) );
    break;

  case E_DFmode:
    if (TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
))
{
 dst = gen_lowpartrtl_hooks.gen_lowpart (DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)), operands[0]);
 dst = gen_rtx_ZERO_EXTRACT (DImode, dst, const1_rtx, GEN_INT (63))gen_rtx_fmt_eee_stat ((ZERO_EXTRACT), (((scalar_int_mode ((scalar_int_mode
::from_int) E_DImode)))), ((dst)), (((const_int_rtx[64 +1])))
, ((gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (63)))) );

 if (code == ABS)
   set = const0_rtx(const_int_rtx[64]);
 else
   set = gen_rtx_NOT (DImode, dst)gen_rtx_fmt_e_stat ((NOT), (((scalar_int_mode ((scalar_int_mode
::from_int) E_DImode)))), ((dst)) );
}
    else
{
 dst = gen_highpart (SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), operands[0]);

 if (code == ABS)
   {
     set = gen_int_mode (0x7fffffff, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)));
     absneg_op = AND;
   }
 else
   {
     set = gen_int_mode (0x80000000, SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)));
     absneg_op = XOR;
   }
 set = gen_rtx_fmt_ee (absneg_op, SImode, dst, set)gen_rtx_fmt_ee_stat ((absneg_op), ((scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), (dst), (set) );
}
    break;

  case E_XFmode:
    dst = gen_rtx_REG (SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)),
	 REGNO (operands[0])(rhs_regno(operands[0])) + (TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
) ? 1 : 2));
    if (code == ABS)
{
 set = GEN_INT (0x7fff)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x7fff));
 absneg_op = AND;
}
    else
{
 set = GEN_INT (0x8000)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x8000));
 absneg_op = XOR;
}
    set = gen_rtx_fmt_ee (absneg_op, SImode, dst, set)gen_rtx_fmt_ee_stat ((absneg_op), ((scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), (dst), (set) );
    break;

  default:
    gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 1849, __FUNCTION__));
  }

set = gen_rtx_SET (dst, set)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dst))
, ((set)) );

rtx clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG))gen_rtx_fmt_e_stat ((CLOBBER), ((((void) 0, E_VOIDmode))), ((
gen_rtx_REG (((void) 0, E_CCmode), 17))) );
rtvec par = gen_rtvec (2, set, clob);

emit_insn (gen_rtx_PARALLEL (VOIDmode, par)gen_rtx_fmt_E_stat ((PARALLEL), ((((void) 0, E_VOIDmode))), (
(par)) ));
1858}

1860/* Expand a copysign operation.  Special case operand 0 being a constant.  */

1862void
1863ix86_expand_copysign (rtx operands[])
1864{
machine_mode mode, vmode;
rtx dest, op0, op1, mask;

dest = operands[0];
op0 = operands[1];
op1 = operands[2];

mode = GET_MODE (dest)((machine_mode) (dest)->mode);

if (mode == SFmode(scalar_float_mode ((scalar_float_mode::from_int) E_SFmode)))
  vmode = V4SFmode((void) 0, E_V4SFmode);
else if (mode == DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)))
  vmode = V2DFmode((void) 0, E_V2DFmode);
else if (mode == TFmode(scalar_float_mode ((scalar_float_mode::from_int) E_TFmode)))
  vmode = mode;
else
  gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 1881, __FUNCTION__));

mask = ix86_build_signbit_mask (vmode, 0, 0);

if (CONST_DOUBLE_P (op0)(((enum rtx_code) (op0)->code) == CONST_DOUBLE))
  {
    if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0)((const struct real_value *) (&(op0)->u.rv))))
op0 = simplify_unary_operation (ABS, mode, op0, mode);

    if (mode == SFmode(scalar_float_mode ((scalar_float_mode::from_int) E_SFmode)) || mode == DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)))
{
 if (op0 == CONST0_RTX (mode)(const_tiny_rtx[0][(int) (mode)]))
   op0 = CONST0_RTX (vmode)(const_tiny_rtx[0][(int) (vmode)]);
 else
   {
     rtx v = ix86_build_const_vector (vmode, false, op0);

     op0 = force_reg (vmode, v);
   }
}
    else if (op0 != CONST0_RTX (mode)(const_tiny_rtx[0][(int) (mode)]))
op0 = force_reg (mode, op0);

    emit_insn (gen_copysign3_const (mode, dest, op0, op1, mask));
  }
else
  {
    rtx nmask = ix86_build_signbit_mask (vmode, 0, 1);

    emit_insn (gen_copysign3_var
 (mode, dest, NULL_RTX(rtx) 0, op0, op1, nmask, mask));
  }
1913}

1915/* Deconstruct a copysign operation into bit masks.  Operand 0 is known to
 be a constant, and so has already been expanded into a vector constant.  */

1918void
1919ix86_split_copysign_const (rtx operands[])
1920{
machine_mode mode, vmode;
rtx dest, op0, mask, x;

dest = operands[0];
op0 = operands[1];
mask = operands[3];

mode = GET_MODE (dest)((machine_mode) (dest)->mode);
vmode = GET_MODE (mask)((machine_mode) (mask)->mode);

dest = lowpart_subreg (vmode, dest, mode);
x = gen_rtx_AND (vmode, dest, mask)gen_rtx_fmt_ee_stat ((AND), ((vmode)), ((dest)), ((mask)) );
emit_insn (gen_rtx_SET (dest, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((x)) ));

if (op0 != CONST0_RTX (vmode)(const_tiny_rtx[0][(int) (vmode)]))
  {
    x = gen_rtx_IOR (vmode, dest, op0)gen_rtx_fmt_ee_stat ((IOR), ((vmode)), ((dest)), ((op0)) );
    emit_insn (gen_rtx_SET (dest, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((x)) ));
  }
1940}

1942/* Deconstruct a copysign operation into bit masks.  Operand 0 is variable,
 so we have to do two masks.  */

1945void
1946ix86_split_copysign_var (rtx operands[])
1947{
machine_mode mode, vmode;
rtx dest, scratch, op0, op1, mask, nmask, x;

dest = operands[0];
scratch = operands[1];
op0 = operands[2];
op1 = operands[3];
nmask = operands[4];
mask = operands[5];

mode = GET_MODE (dest)((machine_mode) (dest)->mode);
vmode = GET_MODE (mask)((machine_mode) (mask)->mode);

if (rtx_equal_p (op0, op1))
  {
    /* Shouldn't happen often (it's useless, obviously), but when it does
we'd generate incorrect code if we continue below.  */
    emit_move_insn (dest, op0);
    return;
  }

if (REG_P (mask)(((enum rtx_code) (mask)->code) == REG) && REGNO (dest)(rhs_regno(dest)) == REGNO (mask)(rhs_regno(mask)))	/* alternative 0 */
  {
    gcc_assert (REGNO (op1) == REGNO (scratch))((void)(!((rhs_regno(op1)) == (rhs_regno(scratch))) ? fancy_abort
 ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 1971, __FUNCTION__), 0 : 0));

    x = gen_rtx_AND (vmode, scratch, mask)gen_rtx_fmt_ee_stat ((AND), ((vmode)), ((scratch)), ((mask)) );
    emit_insn (gen_rtx_SET (scratch, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((scratch
)), ((x)) ));

    dest = mask;
    op0 = lowpart_subreg (vmode, op0, mode);
    x = gen_rtx_NOT (vmode, dest)gen_rtx_fmt_e_stat ((NOT), ((vmode)), ((dest)) );
    x = gen_rtx_AND (vmode, x, op0)gen_rtx_fmt_ee_stat ((AND), ((vmode)), ((x)), ((op0)) );
    emit_insn (gen_rtx_SET (dest, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((x)) ));
  }
else
  {
    if (REGNO (op1)(rhs_regno(op1)) == REGNO (scratch)(rhs_regno(scratch)))		/* alternative 1,3 */
{
 x = gen_rtx_AND (vmode, scratch, mask)gen_rtx_fmt_ee_stat ((AND), ((vmode)), ((scratch)), ((mask)) );
}
    else						/* alternative 2,4 */
{
        gcc_assert (REGNO (mask) == REGNO (scratch))((void)(!((rhs_regno(mask)) == (rhs_regno(scratch))) ? fancy_abort
 ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 1990, __FUNCTION__), 0 : 0));
        op1 = lowpart_subreg (vmode, op1, mode);
 x = gen_rtx_AND (vmode, scratch, op1)gen_rtx_fmt_ee_stat ((AND), ((vmode)), ((scratch)), ((op1)) );
}
    emit_insn (gen_rtx_SET (scratch, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((scratch
)), ((x)) ));

    if (REGNO (op0)(rhs_regno(op0)) == REGNO (dest)(rhs_regno(dest)))			/* alternative 1,2 */
{
 dest = lowpart_subreg (vmode, op0, mode);
 x = gen_rtx_AND (vmode, dest, nmask)gen_rtx_fmt_ee_stat ((AND), ((vmode)), ((dest)), ((nmask)) );
}
    else						/* alternative 3,4 */
{
        gcc_assert (REGNO (nmask) == REGNO (dest))((void)(!((rhs_regno(nmask)) == (rhs_regno(dest))) ? fancy_abort
 ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2003, __FUNCTION__), 0 : 0));
 dest = nmask;
 op0 = lowpart_subreg (vmode, op0, mode);
 x = gen_rtx_AND (vmode, dest, op0)gen_rtx_fmt_ee_stat ((AND), ((vmode)), ((dest)), ((op0)) );
}
    emit_insn (gen_rtx_SET (dest, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((x)) ));
  }

x = gen_rtx_IOR (vmode, dest, scratch)gen_rtx_fmt_ee_stat ((IOR), ((vmode)), ((dest)), ((scratch)) );
emit_insn (gen_rtx_SET (dest, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((x)) ));
2013}

2015/* Expand an xorsign operation.  */

2017void
2018ix86_expand_xorsign (rtx operands[])
2019{
machine_mode mode, vmode;
rtx dest, op0, op1, mask;

dest = operands[0];
op0 = operands[1];
op1 = operands[2];

mode = GET_MODE (dest)((machine_mode) (dest)->mode);

if (mode == SFmode(scalar_float_mode ((scalar_float_mode::from_int) E_SFmode)))
  vmode = V4SFmode((void) 0, E_V4SFmode);
else if (mode == DFmode(scalar_float_mode ((scalar_float_mode::from_int) E_DFmode)))
  vmode = V2DFmode((void) 0, E_V2DFmode);
else
  gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2034, __FUNCTION__));

mask = ix86_build_signbit_mask (vmode, 0, 0);

emit_insn (gen_xorsign3_1 (mode, dest, op0, op1, mask));
2039}

2041/* Deconstruct an xorsign operation into bit masks.  */

2043void
2044ix86_split_xorsign (rtx operands[])
2045{
machine_mode mode, vmode;
rtx dest, op0, mask, x;

dest = operands[0];
op0 = operands[1];
mask = operands[3];

mode = GET_MODE (dest)((machine_mode) (dest)->mode);
vmode = GET_MODE (mask)((machine_mode) (mask)->mode);

dest = lowpart_subreg (vmode, dest, mode);
x = gen_rtx_AND (vmode, dest, mask)gen_rtx_fmt_ee_stat ((AND), ((vmode)), ((dest)), ((mask)) );
emit_insn (gen_rtx_SET (dest, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((x)) ));

op0 = lowpart_subreg (vmode, op0, mode);
x = gen_rtx_XOR (vmode, dest, op0)gen_rtx_fmt_ee_stat ((XOR), ((vmode)), ((dest)), ((op0)) );
emit_insn (gen_rtx_SET (dest, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((x)) ));
2063}

2065static rtx ix86_expand_compare (enum rtx_code code, rtx op0, rtx op1);

2067void
2068ix86_expand_branch (enum rtx_code code, rtx op0, rtx op1, rtx label)
2069{
machine_mode mode = GET_MODE (op0)((machine_mode) (op0)->mode);
rtx tmp;

/* Handle special case - vector comparsion with boolean result, transform
   it using ptest instruction.  */
if (GET_MODE_CLASS (mode)((enum mode_class) mode_class[mode]) == MODE_VECTOR_INT)
  {
    rtx flag = gen_rtx_REG (CCZmode((void) 0, E_CCZmode), FLAGS_REG17);
    machine_mode p_mode = GET_MODE_SIZE (mode)((unsigned short) mode_to_bytes (mode).coeffs[0]) == 32 ? V4DImode((void) 0, E_V4DImode) : V2DImode((void) 0, E_V2DImode);

    gcc_assert (code == EQ || code == NE)((void)(!(code == EQ || code == NE) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2080, __FUNCTION__), 0 : 0));
    /* Generate XOR since we can't check that one operand is zero vector.  */
    tmp = gen_reg_rtx (mode);
    emit_insn (gen_rtx_SET (tmp, gen_rtx_XOR (mode, op0, op1))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((tmp))
, ((gen_rtx_fmt_ee_stat ((XOR), ((mode)), ((op0)), ((op1)) ))
) ));
    tmp = gen_lowpartrtl_hooks.gen_lowpart (p_mode, tmp);
    emit_insn (gen_rtx_SET (gen_rtx_REG (CCmode, FLAGS_REG),gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((gen_rtx_REG
 (((void) 0, E_CCmode), 17))), ((gen_rtx_fmt_Ei_stat ((UNSPEC
), ((((void) 0, E_CCmode))), ((gen_rtvec (2, tmp, tmp))), ((UNSPEC_PTEST
)) ))) )
	      gen_rtx_UNSPEC (CCmode,gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((gen_rtx_REG
 (((void) 0, E_CCmode), 17))), ((gen_rtx_fmt_Ei_stat ((UNSPEC
), ((((void) 0, E_CCmode))), ((gen_rtvec (2, tmp, tmp))), ((UNSPEC_PTEST
)) ))) )
			      gen_rtvec (2, tmp, tmp),gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((gen_rtx_REG
 (((void) 0, E_CCmode), 17))), ((gen_rtx_fmt_Ei_stat ((UNSPEC
), ((((void) 0, E_CCmode))), ((gen_rtvec (2, tmp, tmp))), ((UNSPEC_PTEST
)) ))) )
			      UNSPEC_PTEST))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((gen_rtx_REG
 (((void) 0, E_CCmode), 17))), ((gen_rtx_fmt_Ei_stat ((UNSPEC
), ((((void) 0, E_CCmode))), ((gen_rtvec (2, tmp, tmp))), ((UNSPEC_PTEST
)) ))) ));
    tmp = gen_rtx_fmt_ee (code, VOIDmode, flag, const0_rtx)gen_rtx_fmt_ee_stat ((code), (((void) 0, E_VOIDmode)), (flag)
, ((const_int_rtx[64])) );
    tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((((void) 0, E_VOIDmode
))), ((tmp)), ((gen_rtx_fmt_u_stat ((LABEL_REF), ((((void) 0,
 E_VOIDmode))), ((label)) ))), ((pc_rtx)) )
		  gen_rtx_LABEL_REF (VOIDmode, label),gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((((void) 0, E_VOIDmode
))), ((tmp)), ((gen_rtx_fmt_u_stat ((LABEL_REF), ((((void) 0,
 E_VOIDmode))), ((label)) ))), ((pc_rtx)) )
		  pc_rtx)gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((((void) 0, E_VOIDmode
))), ((tmp)), ((gen_rtx_fmt_u_stat ((LABEL_REF), ((((void) 0,
 E_VOIDmode))), ((label)) ))), ((pc_rtx)) );
    emit_jump_insn (gen_rtx_SET (pc_rtx, tmp)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((pc_rtx
)), ((tmp)) ));
    return;
  }

switch (mode)
  {
  case E_SFmode:
  case E_DFmode:
  case E_XFmode:
  case E_QImode:
  case E_HImode:
  case E_SImode:
    simple:
    tmp = ix86_expand_compare (code, op0, op1);
    tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((((void) 0, E_VOIDmode
))), ((tmp)), ((gen_rtx_fmt_u_stat ((LABEL_REF), ((((void) 0,
 E_VOIDmode))), ((label)) ))), ((pc_rtx)) )
		  gen_rtx_LABEL_REF (VOIDmode, label),gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((((void) 0, E_VOIDmode
))), ((tmp)), ((gen_rtx_fmt_u_stat ((LABEL_REF), ((((void) 0,
 E_VOIDmode))), ((label)) ))), ((pc_rtx)) )
		  pc_rtx)gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((((void) 0, E_VOIDmode
))), ((tmp)), ((gen_rtx_fmt_u_stat ((LABEL_REF), ((((void) 0,
 E_VOIDmode))), ((label)) ))), ((pc_rtx)) );
    emit_jump_insn (gen_rtx_SET (pc_rtx, tmp)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((pc_rtx
)), ((tmp)) ));
    return;

  case E_DImode:
    if (TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
))
goto simple;
    /* For 32-bit target DI comparison may be performed on
SSE registers.  To allow this we should avoid split
to SI mode which is achieved by doing xor in DI mode
and then comparing with zero (which is recognized by
STV pass).  We don't compare using xor when optimizing
for size.  */
    if (!optimize_insn_for_size_p ()
 && TARGET_STV((global_options.x_target_flags & (1U << 26)) != 0)
 && (code == EQ || code == NE))
{
 op0 = force_reg (mode, gen_rtx_XOR (mode, op0, op1)gen_rtx_fmt_ee_stat ((XOR), ((mode)), ((op0)), ((op1)) ));
 op1 = const0_rtx(const_int_rtx[64]);
}
    /* FALLTHRU */
  case E_TImode:
    /* Expand DImode branch into multiple compare+branch.  */
    {
rtx lo[2], hi[2];
rtx_code_label *label2;
enum rtx_code code1, code2, code3;
machine_mode submode;

if (CONSTANT_P (op0)((rtx_class[(int) (((enum rtx_code) (op0)->code))]) == RTX_CONST_OBJ
) && !CONSTANT_P (op1)((rtx_class[(int) (((enum rtx_code) (op1)->code))]) == RTX_CONST_OBJ
))
 {
   std::swap (op0, op1);
   code = swap_condition (code);
 }

split_double_mode (mode, &op0, 1, lo+0, hi+0);
split_double_mode (mode, &op1, 1, lo+1, hi+1);

submode = mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) ? SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)) : DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode));

/* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
  avoid two branches.  This costs one extra insn, so disable when
  optimizing for size.  */

if ((code == EQ || code == NE)
   && (!optimize_insn_for_size_p ()
       || hi[1] == const0_rtx(const_int_rtx[64]) || lo[1] == const0_rtx(const_int_rtx[64])))
 {
   rtx xor0, xor1;

   xor1 = hi[0];
   if (hi[1] != const0_rtx(const_int_rtx[64]))
     xor1 = expand_binop (submode, xor_optab, xor1, hi[1],
		   NULL_RTX(rtx) 0, 0, OPTAB_WIDEN);

   xor0 = lo[0];
   if (lo[1] != const0_rtx(const_int_rtx[64]))
     xor0 = expand_binop (submode, xor_optab, xor0, lo[1],
		   NULL_RTX(rtx) 0, 0, OPTAB_WIDEN);

   tmp = expand_binop (submode, ior_optab, xor1, xor0,
		NULL_RTX(rtx) 0, 0, OPTAB_WIDEN);

   ix86_expand_branch (code, tmp, const0_rtx(const_int_rtx[64]), label);
   return;
 }

/* Otherwise, if we are doing less-than or greater-or-equal-than,
  op1 is a constant and the low word is zero, then we can just
  examine the high word.  Similarly for low word -1 and
  less-or-equal-than or greater-than.  */

if (CONST_INT_P (hi[1])(((enum rtx_code) (hi[1])->code) == CONST_INT))
 switch (code)
   {
   case LT: case LTU: case GE: case GEU:
     if (lo[1] == const0_rtx(const_int_rtx[64]))
{
  ix86_expand_branch (code, hi[0], hi[1], label);
  return;
}
     break;
   case LE: case LEU: case GT: case GTU:
     if (lo[1] == constm1_rtx(const_int_rtx[64 -1]))
{
  ix86_expand_branch (code, hi[0], hi[1], label);
  return;
}
     break;
   default:
     break;
   }

/* Emulate comparisons that do not depend on Zero flag with
  double-word subtraction.  Note that only Overflow, Sign
  and Carry flags are valid, so swap arguments and condition
  of comparisons that would otherwise test Zero flag.  */

switch (code)
 {
 case LE: case LEU: case GT: case GTU:
   std::swap (lo[0], lo[1]);
   std::swap (hi[0], hi[1]);
   code = swap_condition (code);
   /* FALLTHRU */

 case LT: case LTU: case GE: case GEU:
   {
     bool uns = (code == LTU || code == GEU);
     rtx (*sbb_insn) (machine_mode, rtx, rtx, rtx)
= uns ? gen_sub3_carry_ccc : gen_sub3_carry_ccgz;

     if (!nonimmediate_operand (lo[0], submode))
lo[0] = force_reg (submode, lo[0]);
     if (!x86_64_general_operand (lo[1], submode))
lo[1] = force_reg (submode, lo[1]);

     if (!register_operand (hi[0], submode))
hi[0] = force_reg (submode, hi[0]);
     if ((uns && !nonimmediate_operand (hi[1], submode))
  || (!uns && !x86_64_general_operand (hi[1], submode)))
hi[1] = force_reg (submode, hi[1]);

     emit_insn (gen_cmp_1 (submode, lo[0], lo[1]));

     tmp = gen_rtx_SCRATCH (submode)gen_rtx_fmt__stat ((SCRATCH), ((submode)) );
     emit_insn (sbb_insn (submode, tmp, hi[0], hi[1]));

     tmp = gen_rtx_REG (uns ? CCCmode((void) 0, E_CCCmode) : CCGZmode((void) 0, E_CCGZmode), FLAGS_REG17);
     ix86_expand_branch (code, tmp, const0_rtx(const_int_rtx[64]), label);
     return;
   }

 default:
   break;
 }

/* Otherwise, we need two or three jumps.  */

label2 = gen_label_rtx ();

code1 = code;
code2 = swap_condition (code);
code3 = unsigned_condition (code);

switch (code)
 {
 case LT: case GT: case LTU: case GTU:
   break;

 case LE:   code1 = LT;  code2 = GT;  break;
 case GE:   code1 = GT;  code2 = LT;  break;
 case LEU:  code1 = LTU; code2 = GTU; break;
 case GEU:  code1 = GTU; code2 = LTU; break;

 case EQ:   code1 = UNKNOWN; code2 = NE;  break;
 case NE:   code2 = UNKNOWN; break;

 default:
   gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2268, __FUNCTION__));
 }

/*
* a < b =>
*    if (hi(a) < hi(b)) goto true;
*    if (hi(a) > hi(b)) goto false;
*    if (lo(a) < lo(b)) goto true;
*  false:
*/

if (code1 != UNKNOWN)
 ix86_expand_branch (code1, hi[0], hi[1], label);
if (code2 != UNKNOWN)
 ix86_expand_branch (code2, hi[0], hi[1], label2);

ix86_expand_branch (code3, lo[0], lo[1], label);

if (code2 != UNKNOWN)
 emit_label (label2);
return;
    }

  default:
    gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)((void)(!(((enum mode_class) mode_class[((machine_mode) (op0)
->mode)]) == MODE_CC) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2292, __FUNCTION__), 0 : 0));
    goto simple;
  }
2295}

2297/* Figure out whether to use unordered fp comparisons.  */

2299static bool
2300ix86_unordered_fp_compare (enum rtx_code code)
2301{
if (!TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0))
  return false;

switch (code)
  {
  case LT:
  case LE:
  case GT:
  case GE:
  case LTGT:
    return false;

  case EQ:
  case NE:

  case UNORDERED:
  case ORDERED:
  case UNLT:
  case UNLE:
  case UNGT:
  case UNGE:
  case UNEQ:
    return true;

  default:
    gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2327, __FUNCTION__));
  }
2329}

2331/* Return a comparison we can do and that it is equivalent to
 swap_condition (code) apart possibly from orderedness.
 But, never change orderedness if TARGET_IEEE_FP, returning
 UNKNOWN in that case if necessary.  */

2336static enum rtx_code
2337ix86_fp_swap_condition (enum rtx_code code)
2338{
switch (code)
  {
  case GT:                   /* GTU - CF=0 & ZF=0 */
    return TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0) ? UNKNOWN : UNLT;
  case GE:                   /* GEU - CF=0 */
    return TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0) ? UNKNOWN : UNLE;
  case UNLT:                 /* LTU - CF=1 */
    return TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0) ? UNKNOWN : GT;
  case UNLE:                 /* LEU - CF=1 | ZF=1 */
    return TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0) ? UNKNOWN : GE;
  default:
    return swap_condition (code);
  }
2352}

2354/* Return cost of comparison CODE using the best strategy for performance.
 All following functions do use number of instructions as a cost metrics.
 In future this should be tweaked to compute bytes for optimize_size and
 take into account performance of various instructions on various CPUs.  */

2359static int
2360ix86_fp_comparison_cost (enum rtx_code code)
2361{
int arith_cost;

/* The cost of code using bit-twiddling on %ah.  */
switch (code)
  {
  case UNLE:
  case UNLT:
  case LTGT:
  case GT:
  case GE:
  case UNORDERED:
  case ORDERED:
  case UNEQ:
    arith_cost = 4;
    break;
  case LT:
  case NE:
  case EQ:
  case UNGE:
    arith_cost = TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0) ? 5 : 4;
    break;
  case LE:
  case UNGT:
    arith_cost = TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0) ? 6 : 4;
    break;
  default:
    gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2388, __FUNCTION__));
  }

switch (ix86_fp_comparison_strategy (code))
  {
  case IX86_FPCMP_COMI:
    return arith_cost > 4 ? 3 : 2;
  case IX86_FPCMP_SAHF:
    return arith_cost > 4 ? 4 : 3;
  default:
    return arith_cost;
  }
2400}

2402/* Swap, force into registers, or otherwise massage the two operands
 to a fp comparison.  The operands are updated in place; the new
 comparison code is returned.  */

2406static enum rtx_code
2407ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1)
2408{
bool unordered_compare = ix86_unordered_fp_compare (code);
rtx op0 = *pop0, op1 = *pop1;
machine_mode op_mode = GET_MODE (op0)((machine_mode) (op0)->mode);
bool is_sse = TARGET_SSE_MATH((global_options.x_ix86_fpmath & FPMATH_SSE) != 0) && SSE_FLOAT_MODE_P (op_mode)((((global_options.x_ix86_isa_flags & (1UL << 50)) !=
 0) && (op_mode) == (scalar_float_mode ((scalar_float_mode
::from_int) E_SFmode))) || (((global_options.x_ix86_isa_flags
 & (1UL << 51)) != 0) && (op_mode) == (scalar_float_mode
 ((scalar_float_mode::from_int) E_DFmode))));

/* All of the unordered compare instructions only work on registers.
   The same is true of the fcomi compare instructions.  The XFmode
   compare instructions require registers except when comparing
   against zero or when converting operand 1 from fixed point to
   floating point.  */

if (!is_sse
    && (unordered_compare
 || (op_mode == XFmode(scalar_float_mode ((scalar_float_mode::from_int) E_XFmode))
     && ! (standard_80387_constant_p (op0) == 1
    || standard_80387_constant_p (op1) == 1)
     && GET_CODE (op1)((enum rtx_code) (op1)->code) != FLOAT)
 || ix86_fp_comparison_strategy (code) == IX86_FPCMP_COMI))
  {
    op0 = force_reg (op_mode, op0);
    op1 = force_reg (op_mode, op1);
  }
else
  {
    /* %%% We only allow op1 in memory; op0 must be st(0).  So swap
things around if they appear profitable, otherwise force op0
into a register.  */

    if (standard_80387_constant_p (op0) == 0
 || (MEM_P (op0)(((enum rtx_code) (op0)->code) == MEM)
     && ! (standard_80387_constant_p (op1) == 0
    || MEM_P (op1)(((enum rtx_code) (op1)->code) == MEM))))
{
 enum rtx_code new_code = ix86_fp_swap_condition (code);
 if (new_code != UNKNOWN)
   {
     std::swap (op0, op1);
     code = new_code;
   }
}

    if (!REG_P (op0)(((enum rtx_code) (op0)->code) == REG))
op0 = force_reg (op_mode, op0);

    if (CONSTANT_P (op1)((rtx_class[(int) (((enum rtx_code) (op1)->code))]) == RTX_CONST_OBJ
))
{
 int tmp = standard_80387_constant_p (op1);
 if (tmp == 0)
   op1 = validize_mem (force_const_mem (op_mode, op1));
 else if (tmp == 1)
   {
     if (TARGET_CMOVE(ix86_arch_features[X86_ARCH_CMOV] || ((global_options.x_ix86_isa_flags
 & (1UL << 50)) != 0) || ((global_options.x_ix86_isa_flags
 & (1UL << 44)) != 0)))
op1 = force_reg (op_mode, op1);
   }
 else
   op1 = force_reg (op_mode, op1);
}
  }

/* Try to rearrange the comparison to make it cheaper.  */
if (ix86_fp_comparison_cost (code)
    > ix86_fp_comparison_cost (swap_condition (code))
    && (REG_P (op1)(((enum rtx_code) (op1)->code) == REG) || can_create_pseudo_p ()(!reload_in_progress && !reload_completed)))
  {
    std::swap (op0, op1);
    code = swap_condition (code);
    if (!REG_P (op0)(((enum rtx_code) (op0)->code) == REG))
op0 = force_reg (op_mode, op0);
  }

*pop0 = op0;
*pop1 = op1;
return code;
2482}

2484/* Generate insn patterns to do a floating point compare of OPERANDS.  */

2486static rtx
2487ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1)
2488{
bool unordered_compare = ix86_unordered_fp_compare (code);
machine_mode cmp_mode;
rtx tmp, scratch;

code = ix86_prepare_fp_compare_args (code, &op0, &op1);

tmp = gen_rtx_COMPARE (CCFPmode, op0, op1)gen_rtx_fmt_ee_stat ((COMPARE), ((((void) 0, E_CCFPmode))), (
(op0)), ((op1)) );
if (unordered_compare)
  tmp = gen_rtx_UNSPEC (CCFPmode, gen_rtvec (1, tmp), UNSPEC_NOTRAP)gen_rtx_fmt_Ei_stat ((UNSPEC), ((((void) 0, E_CCFPmode))), ((
gen_rtvec (1, tmp))), ((UNSPEC_NOTRAP)) );

/* Do fcomi/sahf based test when profitable.  */
switch (ix86_fp_comparison_strategy (code))
  {
  case IX86_FPCMP_COMI:
    cmp_mode = CCFPmode((void) 0, E_CCFPmode);
    emit_insn (gen_rtx_SET (gen_rtx_REG (CCFPmode, FLAGS_REG), tmp)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((gen_rtx_REG
 (((void) 0, E_CCFPmode), 17))), ((tmp)) ));
    break;

  case IX86_FPCMP_SAHF:
    cmp_mode = CCFPmode((void) 0, E_CCFPmode);
    tmp = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW)gen_rtx_fmt_Ei_stat ((UNSPEC), (((scalar_int_mode ((scalar_int_mode
::from_int) E_HImode)))), ((gen_rtvec (1, tmp))), ((UNSPEC_FNSTSW
)) );
    scratch = gen_reg_rtx (HImode(scalar_int_mode ((scalar_int_mode::from_int) E_HImode)));
    emit_insn (gen_rtx_SET (scratch, tmp)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((scratch
)), ((tmp)) ));
    emit_insn (gen_x86_sahf_1 (scratch));
    break;

  case IX86_FPCMP_ARITH:
    cmp_mode = CCNOmode((void) 0, E_CCNOmode);
    tmp = gen_rtx_UNSPEC (HImode, gen_rtvec (1, tmp), UNSPEC_FNSTSW)gen_rtx_fmt_Ei_stat ((UNSPEC), (((scalar_int_mode ((scalar_int_mode
::from_int) E_HImode)))), ((gen_rtvec (1, tmp))), ((UNSPEC_FNSTSW
)) );
    scratch = gen_reg_rtx (HImode(scalar_int_mode ((scalar_int_mode::from_int) E_HImode)));
    emit_insn (gen_rtx_SET (scratch, tmp)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((scratch
)), ((tmp)) ));

    /* In the unordered case, we have to check C2 for NaN's, which
doesn't happen to work out to anything nice combination-wise.
So do some bit twiddling on the value we've got in AH to come
up with an appropriate set of condition codes.  */

    switch (code)
{
case GT:
case UNGT:
 if (code == GT || !TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0))
   {
     emit_insn (gen_testqi_ext_1_ccno (scratch, GEN_INT (0x45)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x45))));
     code = EQ;
   }
 else
   {
     emit_insn (gen_andqi_ext_1 (scratch, scratch, GEN_INT (0x45)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x45))));
     emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx(const_int_rtx[64 -1])));
     emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x44)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x44))));
     cmp_mode = CCmode((void) 0, E_CCmode);
     code = GEU;
   }
 break;
case LT:
case UNLT:
 if (code == LT && TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0))
   {
     emit_insn (gen_andqi_ext_1 (scratch, scratch, GEN_INT (0x45)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x45))));
     emit_insn (gen_cmpqi_ext_3 (scratch, const1_rtx(const_int_rtx[64 +1])));
     cmp_mode = CCmode((void) 0, E_CCmode);
     code = EQ;
   }
 else
   {
     emit_insn (gen_testqi_ext_1_ccno (scratch, const1_rtx(const_int_rtx[64 +1])));
     code = NE;
   }
 break;
case GE:
case UNGE:
 if (code == GE || !TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0))
   {
     emit_insn (gen_testqi_ext_1_ccno (scratch, GEN_INT (0x05)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x05))));
     code = EQ;
   }
 else
   {
     emit_insn (gen_andqi_ext_1 (scratch, scratch, GEN_INT (0x45)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x45))));
     emit_insn (gen_xorqi_ext_1_cc (scratch, scratch, const1_rtx(const_int_rtx[64 +1])));
     code = NE;
   }
 break;
case LE:
case UNLE:
 if (code == LE && TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0))
   {
     emit_insn (gen_andqi_ext_1 (scratch, scratch, GEN_INT (0x45)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x45))));
     emit_insn (gen_addqi_ext_1 (scratch, scratch, constm1_rtx(const_int_rtx[64 -1])));
     emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x40))));
     cmp_mode = CCmode((void) 0, E_CCmode);
     code = LTU;
   }
 else
   {
     emit_insn (gen_testqi_ext_1_ccno (scratch, GEN_INT (0x45)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x45))));
     code = NE;
   }
 break;
case EQ:
case UNEQ:
 if (code == EQ && TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0))
   {
     emit_insn (gen_andqi_ext_1 (scratch, scratch, GEN_INT (0x45)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x45))));
     emit_insn (gen_cmpqi_ext_3 (scratch, GEN_INT (0x40)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x40))));
     cmp_mode = CCmode((void) 0, E_CCmode);
     code = EQ;
   }
 else
   {
     emit_insn (gen_testqi_ext_1_ccno (scratch, GEN_INT (0x40)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x40))));
     code = NE;
   }
 break;
case NE:
case LTGT:
 if (code == NE && TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0))
   {
     emit_insn (gen_andqi_ext_1 (scratch, scratch, GEN_INT (0x45)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x45))));
     emit_insn (gen_xorqi_ext_1_cc (scratch, scratch,
			     GEN_INT (0x40)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x40))));
     code = NE;
   }
 else
   {
     emit_insn (gen_testqi_ext_1_ccno (scratch, GEN_INT (0x40)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x40))));
     code = EQ;
   }
 break;

case UNORDERED:
 emit_insn (gen_testqi_ext_1_ccno (scratch, GEN_INT (0x04)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x04))));
 code = NE;
 break;
case ORDERED:
 emit_insn (gen_testqi_ext_1_ccno (scratch, GEN_INT (0x04)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (0x04))));
 code = EQ;
 break;

default:
 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2630, __FUNCTION__));
}
break;

  default:
    gcc_unreachable()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2635, __FUNCTION__));
  }

/* Return the test that should be put into the flags user, i.e.
   the bcc, scc, or cmov instruction.  */
return gen_rtx_fmt_ee (code, VOIDmode,gen_rtx_fmt_ee_stat ((code), (((void) 0, E_VOIDmode)), (gen_rtx_REG
 (cmp_mode, 17)), ((const_int_rtx[64])) )
	 gen_rtx_REG (cmp_mode, FLAGS_REG),gen_rtx_fmt_ee_stat ((code), (((void) 0, E_VOIDmode)), (gen_rtx_REG
 (cmp_mode, 17)), ((const_int_rtx[64])) )
	 const0_rtx)gen_rtx_fmt_ee_stat ((code), (((void) 0, E_VOIDmode)), (gen_rtx_REG
 (cmp_mode, 17)), ((const_int_rtx[64])) );
2643}

2645/* Generate insn patterns to do an integer compare of OPERANDS.  */

2647static rtx
2648ix86_expand_int_compare (enum rtx_code code, rtx op0, rtx op1)
2649{
machine_mode cmpmode;
rtx tmp, flags;

cmpmode = SELECT_CC_MODE (code, op0, op1)ix86_cc_mode ((code), (op0), (op1));
flags = gen_rtx_REG (cmpmode, FLAGS_REG17);

/* This is very simple, but making the interface the same as in the
   FP case makes the rest of the code easier.  */
tmp = gen_rtx_COMPARE (cmpmode, op0, op1)gen_rtx_fmt_ee_stat ((COMPARE), ((cmpmode)), ((op0)), ((op1))
 );
emit_insn (gen_rtx_SET (flags, tmp)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((flags
)), ((tmp)) ));

/* Return the test that should be put into the flags user, i.e.
   the bcc, scc, or cmov instruction.  */
return gen_rtx_fmt_ee (code, VOIDmode, flags, const0_rtx)gen_rtx_fmt_ee_stat ((code), (((void) 0, E_VOIDmode)), (flags
), ((const_int_rtx[64])) );
2664}

2666static rtx
2667ix86_expand_compare (enum rtx_code code, rtx op0, rtx op1)
2668{
rtx ret;

if (GET_MODE_CLASS (GET_MODE (op0))((enum mode_class) mode_class[((machine_mode) (op0)->mode)
]) == MODE_CC)
  ret = gen_rtx_fmt_ee (code, VOIDmode, op0, op1)gen_rtx_fmt_ee_stat ((code), (((void) 0, E_VOIDmode)), (op0),
 (op1) );

else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0))(((enum mode_class) mode_class[((machine_mode) (op0)->mode
)]) == MODE_FLOAT || ((enum mode_class) mode_class[((machine_mode
) (op0)->mode)]) == MODE_DECIMAL_FLOAT))
  {
    gcc_assert (!DECIMAL_FLOAT_MODE_P (GET_MODE (op0)))((void)(!(!(((enum mode_class) mode_class[((machine_mode) (op0
)->mode)]) == MODE_DECIMAL_FLOAT)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2676, __FUNCTION__), 0 : 0));
    ret = ix86_expand_fp_compare (code, op0, op1);
  }
else
  ret = ix86_expand_int_compare (code, op0, op1);

return ret;
2683}

2685void
2686ix86_expand_setcc (rtx dest, enum rtx_code code, rtx op0, rtx op1)
2687{
rtx ret;

gcc_assert (GET_MODE (dest) == QImode)((void)(!(((machine_mode) (dest)->mode) == (scalar_int_mode
 ((scalar_int_mode::from_int) E_QImode))) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2690, __FUNCTION__), 0 : 0));

ret = ix86_expand_compare (code, op0, op1);
PUT_MODE (ret, QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)));
emit_insn (gen_rtx_SET (dest, ret)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((ret)) ));
2695}

2697/* Expand comparison setting or clearing carry flag.  Return true when
 successful and set pop for the operation.  */
2699static bool
2700ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
2701{
machine_mode mode
  = GET_MODE (op0)((machine_mode) (op0)->mode) != VOIDmode((void) 0, E_VOIDmode) ? GET_MODE (op0)((machine_mode) (op0)->mode) : GET_MODE (op1)((machine_mode) (op1)->mode);

/* Do not handle double-mode compares that go through special path.  */
if (mode == (TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
) ? TImode(scalar_int_mode ((scalar_int_mode::from_int) E_TImode)) : DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode))))
  return false;

if (SCALAR_FLOAT_MODE_P (mode)(((enum mode_class) mode_class[mode]) == MODE_FLOAT || ((enum
 mode_class) mode_class[mode]) == MODE_DECIMAL_FLOAT))
  {
    rtx compare_op;
    rtx_insn *compare_seq;

    gcc_assert (!DECIMAL_FLOAT_MODE_P (mode))((void)(!(!(((enum mode_class) mode_class[mode]) == MODE_DECIMAL_FLOAT
)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2714, __FUNCTION__), 0 : 0));

    /* Shortcut:  following common codes never translate
into carry flag compares.  */
    if (code == EQ || code == NE || code == UNEQ || code == LTGT
 || code == ORDERED || code == UNORDERED)
return false;

    /* These comparisons require zero flag; swap operands so they won't.  */
    if ((code == GT || code == UNLE || code == LE || code == UNGT)
 && !TARGET_IEEE_FP((global_options.x_target_flags & (1U << 13)) != 0))
{
 std::swap (op0, op1);
 code = swap_condition (code);
}

    /* Try to expand the comparison and verify that we end up with
carry flag based comparison.  This fails to be true only when
we decide to expand comparison using arithmetic that is not
too common scenario.  */
    start_sequence ();
    compare_op = ix86_expand_fp_compare (code, op0, op1);
    compare_seq = get_insns ();
    end_sequence ();

    if (GET_MODE (XEXP (compare_op, 0))((machine_mode) ((((compare_op)->u.fld[0]).rt_rtx))->mode
) == CCFPmode((void) 0, E_CCFPmode))
      code = ix86_fp_compare_code_to_integer (GET_CODE (compare_op)((enum rtx_code) (compare_op)->code));
    else
code = GET_CODE (compare_op)((enum rtx_code) (compare_op)->code);

    if (code != LTU && code != GEU)
return false;

    emit_insn (compare_seq);
    *pop = compare_op;
    return true;
  }

if (!INTEGRAL_MODE_P (mode)(((enum mode_class) mode_class[mode]) == MODE_INT || ((enum mode_class
) mode_class[mode]) == MODE_PARTIAL_INT || ((enum mode_class)
 mode_class[mode]) == MODE_COMPLEX_INT || ((enum mode_class) mode_class
[mode]) == MODE_VECTOR_BOOL || ((enum mode_class) mode_class[
mode]) == MODE_VECTOR_INT))
  return false;

switch (code)
  {
  case LTU:
  case GEU:
    break;

  /* Convert a==0 into (unsigned)a<1.  */
  case EQ:
  case NE:
    if (op1 != const0_rtx(const_int_rtx[64]))
return false;
    op1 = const1_rtx(const_int_rtx[64 +1]);
    code = (code == EQ ? LTU : GEU);
    break;

  /* Convert a>b into b<a or a>=b-1.  */
  case GTU:
  case LEU:
    if (CONST_INT_P (op1)(((enum rtx_code) (op1)->code) == CONST_INT))
{
 op1 = gen_int_mode (INTVAL (op1)((op1)->u.hwint[0]) + 1, GET_MODE (op0)((machine_mode) (op0)->mode));
 /* Bail out on overflow.  We still can swap operands but that
    would force loading of the constant into register.  */
 if (op1 == const0_rtx(const_int_rtx[64])
     || !x86_64_immediate_operand (op1, GET_MODE (op1)((machine_mode) (op1)->mode)))
   return false;
 code = (code == GTU ? GEU : LTU);
}
    else
{
 std::swap (op0, op1);
 code = (code == GTU ? LTU : GEU);
}
    break;

  /* Convert a>=0 into (unsigned)a<0x80000000.  */
  case LT:
  case GE:
    if (mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) || op1 != const0_rtx(const_int_rtx[64]))
return false;
    op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode)((unsigned short) mode_to_bits (mode).coeffs[0]) - 1), mode);
    code = (code == LT ? GEU : LTU);
    break;
  case LE:
  case GT:
    if (mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) || op1 != constm1_rtx(const_int_rtx[64 -1]))
return false;
    op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode)((unsigned short) mode_to_bits (mode).coeffs[0]) - 1), mode);
    code = (code == LE ? GEU : LTU);
    break;

  default:
    return false;
  }
/* Swapping operands may cause constant to appear as first operand.  */
if (!nonimmediate_operand (op0, VOIDmode((void) 0, E_VOIDmode)))
  {
    if (!can_create_pseudo_p ()(!reload_in_progress && !reload_completed))
return false;
    op0 = force_reg (mode, op0);
  }
*pop = ix86_expand_compare (code, op0, op1);
gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU)((void)(!(((enum rtx_code) (*pop)->code) == LTU || ((enum rtx_code
) (*pop)->code) == GEU) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 2817, __FUNCTION__), 0 : 0));
return true;
2819}

2821/* Expand conditional increment or decrement using adb/sbb instructions.
 The default case using setcc followed by the conditional move can be
 done by generic code.  */
2824bool
2825ix86_expand_int_addcc (rtx operands[])
2826{
enum rtx_code code = GET_CODE (operands[1])((enum rtx_code) (operands[1])->code);
rtx flags;
rtx (*insn) (machine_mode, rtx, rtx, rtx, rtx, rtx);
rtx compare_op;
rtx val = const0_rtx(const_int_rtx[64]);
bool fpcmp = false;
machine_mode mode;
rtx op0 = XEXP (operands[1], 0)(((operands[1])->u.fld[0]).rt_rtx);
rtx op1 = XEXP (operands[1], 1)(((operands[1])->u.fld[1]).rt_rtx);

if (operands[3] != const1_rtx(const_int_rtx[64 +1])
    && operands[3] != constm1_rtx(const_int_rtx[64 -1]))
  return false;
if (!ix86_expand_carry_flag_compare (code, op0, op1, &compare_op))
   return false;
code = GET_CODE (compare_op)((enum rtx_code) (compare_op)->code);

flags = XEXP (compare_op, 0)(((compare_op)->u.fld[0]).rt_rtx);

if (GET_MODE (flags)((machine_mode) (flags)->mode) == CCFPmode((void) 0, E_CCFPmode))
  {
    fpcmp = true;
    code = ix86_fp_compare_code_to_integer (code);
  }

if (code != LTU)
  {
    val = constm1_rtx(const_int_rtx[64 -1]);
    if (fpcmp)
PUT_CODE (compare_op,((compare_op)->code = (reverse_condition_maybe_unordered (
((enum rtx_code) (compare_op)->code))))
  reverse_condition_maybe_unordered((compare_op)->code = (reverse_condition_maybe_unordered (
((enum rtx_code) (compare_op)->code))))
    (GET_CODE (compare_op)))((compare_op)->code = (reverse_condition_maybe_unordered (
((enum rtx_code) (compare_op)->code))));
    else
PUT_CODE (compare_op, reverse_condition (GET_CODE (compare_op)))((compare_op)->code = (reverse_condition (((enum rtx_code)
 (compare_op)->code))));
  }

mode = GET_MODE (operands[0])((machine_mode) (operands[0])->mode);

/* Construct either adc or sbb insn.  */
if ((code == LTU) == (operands[3] == constm1_rtx(const_int_rtx[64 -1])))
  insn = gen_sub3_carry;
else
  insn = gen_add3_carry;

emit_insn (insn (mode, operands[0], operands[2], val, flags, compare_op));

return true;
2874}

2876bool
2877ix86_expand_int_movcc (rtx operands[])
2878{
enum rtx_code code = GET_CODE (operands[1])((enum rtx_code) (operands[1])->code), compare_code;
rtx_insn *compare_seq;
rtx compare_op;
machine_mode mode = GET_MODE (operands[0])((machine_mode) (operands[0])->mode);
bool sign_bit_compare_p = false;
rtx op0 = XEXP (operands[1], 0)(((operands[1])->u.fld[0]).rt_rtx);
rtx op1 = XEXP (operands[1], 1)(((operands[1])->u.fld[1]).rt_rtx);

if (GET_MODE (op0)((machine_mode) (op0)->mode) == TImode(scalar_int_mode ((scalar_int_mode::from_int) E_TImode))
    || (GET_MODE (op0)((machine_mode) (op0)->mode) == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode))
 && !TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
)))
  return false;

start_sequence ();
compare_op = ix86_expand_compare (code, op0, op1);
compare_seq = get_insns ();
end_sequence ();

compare_code = GET_CODE (compare_op)((enum rtx_code) (compare_op)->code);

if ((op1 == const0_rtx(const_int_rtx[64]) && (code == GE || code == LT))
    || (op1 == constm1_rtx(const_int_rtx[64 -1]) && (code == GT || code == LE)))
  sign_bit_compare_p = true;

/* Don't attempt mode expansion here -- if we had to expand 5 or 6
   HImode insns, we'd be swallowed in word prefix ops.  */

if ((mode != HImode(scalar_int_mode ((scalar_int_mode::from_int) E_HImode)) || TARGET_FAST_PREFIXix86_tune_features[X86_TUNE_FAST_PREFIX])
    && (mode != (TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
) ? TImode(scalar_int_mode ((scalar_int_mode::from_int) E_TImode)) : DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode))))
    && CONST_INT_P (operands[2])(((enum rtx_code) (operands[2])->code) == CONST_INT)
    && CONST_INT_P (operands[3])(((enum rtx_code) (operands[3])->code) == CONST_INT))
  {
    rtx out = operands[0];
    HOST_WIDE_INTlong ct = INTVAL (operands[2])((operands[2])->u.hwint[0]);
    HOST_WIDE_INTlong cf = INTVAL (operands[3])((operands[3])->u.hwint[0]);
    HOST_WIDE_INTlong diff;

    diff = ct - cf;
    /*  Sign bit compares are better done using shifts than we do by using
 sbb.  */
    if (sign_bit_compare_p
 || ix86_expand_carry_flag_compare (code, op0, op1, &compare_op))
{
 /* Detect overlap between destination and compare sources.  */
 rtx tmp = out;

        if (!sign_bit_compare_p)
   {
     rtx flags;
     bool fpcmp = false;

     compare_code = GET_CODE (compare_op)((enum rtx_code) (compare_op)->code);

     flags = XEXP (compare_op, 0)(((compare_op)->u.fld[0]).rt_rtx);

     if (GET_MODE (flags)((machine_mode) (flags)->mode) == CCFPmode((void) 0, E_CCFPmode))
{
  fpcmp = true;
  compare_code
    = ix86_fp_compare_code_to_integer (compare_code);
}

     /* To simplify rest of code, restrict to the GEU case.  */
     if (compare_code == LTU)
{
  std::swap (ct, cf);
  compare_code = reverse_condition (compare_code);
  code = reverse_condition (code);
}
     else
{
  if (fpcmp)
    PUT_CODE (compare_op,((compare_op)->code = (reverse_condition_maybe_unordered (
((enum rtx_code) (compare_op)->code))))
	      reverse_condition_maybe_unordered((compare_op)->code = (reverse_condition_maybe_unordered (
((enum rtx_code) (compare_op)->code))))
	        (GET_CODE (compare_op)))((compare_op)->code = (reverse_condition_maybe_unordered (
((enum rtx_code) (compare_op)->code))));
  else
    PUT_CODE (compare_op,((compare_op)->code = (reverse_condition (((enum rtx_code)
 (compare_op)->code))))
	      reverse_condition (GET_CODE (compare_op)))((compare_op)->code = (reverse_condition (((enum rtx_code)
 (compare_op)->code))));
}
     diff = ct - cf;

     if (reg_overlap_mentioned_p (out, op0)
  || reg_overlap_mentioned_p (out, op1))
tmp = gen_reg_rtx (mode);

     if (mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)))
emit_insn (gen_x86_movdicc_0_m1 (tmp, flags, compare_op));
     else
emit_insn (gen_x86_movsicc_0_m1	(gen_lowpartrtl_hooks.gen_lowpart (SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), tmp),
				 flags, compare_op));
   }
 else
   {
     if (code == GT || code == GE)
code = reverse_condition (code);
     else
{
  std::swap (ct, cf);
  diff = ct - cf;
}
     tmp = emit_store_flag (tmp, code, op0, op1, VOIDmode((void) 0, E_VOIDmode), 0, -1);
   }

 if (diff == 1)
   {
     /*
      * cmpl op0,op1
      * sbbl dest,dest
      * [addl dest, ct]
      *
      * Size 5 - 8.
      */
     if (ct)
tmp = expand_simple_binop (mode, PLUS,
			   tmp, GEN_INT (ct)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (ct)),
			   copy_rtx (tmp), 1, OPTAB_DIRECT);
   }
 else if (cf == -1)
   {
     /*
      * cmpl op0,op1
      * sbbl dest,dest
      * orl $ct, dest
      *
      * Size 8.
      */
     tmp = expand_simple_binop (mode, IOR,
			 tmp, GEN_INT (ct)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (ct)),
			 copy_rtx (tmp), 1, OPTAB_DIRECT);
   }
 else if (diff == -1 && ct)
   {
     /*
      * cmpl op0,op1
      * sbbl dest,dest
      * notl dest
      * [addl dest, cf]
      *
      * Size 8 - 11.
      */
     tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
     if (cf)
tmp = expand_simple_binop (mode, PLUS,
			   copy_rtx (tmp), GEN_INT (cf)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (cf)),
			   copy_rtx (tmp), 1, OPTAB_DIRECT);
   }
 else
   {
     /*
      * cmpl op0,op1
      * sbbl dest,dest
      * [notl dest]
      * andl cf - ct, dest
      * [addl dest, ct]
      *
      * Size 8 - 11.
      */

     if (cf == 0)
{
  cf = ct;
  ct = 0;
  tmp = expand_simple_unop (mode, NOT, tmp, copy_rtx (tmp), 1);
}

     tmp = expand_simple_binop (mode, AND,
			 copy_rtx (tmp),
			 gen_int_mode (cf - ct, mode),
			 copy_rtx (tmp), 1, OPTAB_DIRECT);
     if (ct)
tmp = expand_simple_binop (mode, PLUS,
			   copy_rtx (tmp), GEN_INT (ct)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (ct)),
			   copy_rtx (tmp), 1, OPTAB_DIRECT);
   }

 if (!rtx_equal_p (tmp, out))
   emit_move_insn (copy_rtx (out), copy_rtx (tmp));

 return true;
}

    if (diff < 0)
{
 machine_mode cmp_mode = GET_MODE (op0)((machine_mode) (op0)->mode);
 enum rtx_code new_code;

 if (SCALAR_FLOAT_MODE_P (cmp_mode)(((enum mode_class) mode_class[cmp_mode]) == MODE_FLOAT || ((
enum mode_class) mode_class[cmp_mode]) == MODE_DECIMAL_FLOAT))
   {
     gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode))((void)(!(!(((enum mode_class) mode_class[cmp_mode]) == MODE_DECIMAL_FLOAT
)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 3067, __FUNCTION__), 0 : 0));

     /* We may be reversing a non-trapping
 comparison to a trapping comparison.  */
  if (HONOR_NANS (cmp_mode) && flag_trapping_mathglobal_options.x_flag_trapping_math
      && code != EQ && code != NE
      && code != ORDERED && code != UNORDERED)
    new_code = UNKNOWN;
  else
    new_code = reverse_condition_maybe_unordered (code);
   }
 else
   new_code = ix86_reverse_condition (code, cmp_mode);
 if (new_code != UNKNOWN)
   {
     std::swap (ct, cf);
     diff = -diff;
     code = new_code;
   }
}

    compare_code = UNKNOWN;
    if (GET_MODE_CLASS (GET_MODE (op0))((enum mode_class) mode_class[((machine_mode) (op0)->mode)
]) == MODE_INT
 && CONST_INT_P (op1)(((enum rtx_code) (op1)->code) == CONST_INT))
{
 if (op1 == const0_rtx(const_int_rtx[64])
     && (code == LT || code == GE))
   compare_code = code;
 else if (op1 == constm1_rtx(const_int_rtx[64 -1]))
   {
     if (code == LE)
compare_code = LT;
     else if (code == GT)
compare_code = GE;
   }
}

    /* Optimize dest = (op0 < 0) ? -1 : cf.  */
    if (compare_code != UNKNOWN
 && GET_MODE (op0)((machine_mode) (op0)->mode) == GET_MODE (out)((machine_mode) (out)->mode)
 && (cf == -1 || ct == -1))
{
 /* If lea code below could be used, only optimize
    if it results in a 2 insn sequence.  */

 if (! (diff == 1 || diff == 2 || diff == 4 || diff == 8
 || diff == 3 || diff == 5 || diff == 9)
     || (compare_code == LT && ct == -1)
     || (compare_code == GE && cf == -1))
   {
     /*
      * notl op1	(if necessary)
      * sarl $31, op1
      * orl cf, op1
      */
     if (ct != -1)
{
  cf = ct;
  ct = -1;
  code = reverse_condition (code);
}

     out = emit_store_flag (out, code, op0, op1, VOIDmode((void) 0, E_VOIDmode), 0, -1);

     out = expand_simple_binop (mode, IOR,
			 out, GEN_INT (cf)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (cf)),
			 out, 1, OPTAB_DIRECT);
     if (out != operands[0])
emit_move_insn (operands[0], out);

     return true;
   }
}


    if ((diff == 1 || diff == 2 || diff == 4 || diff == 8
  || diff == 3 || diff == 5 || diff == 9)
 && ((mode != QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)) && mode != HImode(scalar_int_mode ((scalar_int_mode::from_int) E_HImode))) || !TARGET_PARTIAL_REG_STALLix86_tune_features[X86_TUNE_PARTIAL_REG_STALL])
 && (mode != DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode))
     || x86_64_immediate_operand (GEN_INT (cf)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (cf)), VOIDmode((void) 0, E_VOIDmode))))
{
 /*
  * xorl dest,dest
  * cmpl op1,op2
  * setcc dest
  * lea cf(dest*(ct-cf)),dest
  *
  * Size 14.
  *
  * This also catches the degenerate setcc-only case.
  */

 rtx tmp;
 int nops;

 out = emit_store_flag (out, code, op0, op1, VOIDmode((void) 0, E_VOIDmode), 0, 1);

 nops = 0;
 /* On x86_64 the lea instruction operates on Pmode, so we need
    to get arithmetics done in proper mode to match.  */
 if (diff == 1)
   tmp = copy_rtx (out);
 else
   {
     rtx out1;
     out1 = copy_rtx (out);
     tmp = gen_rtx_MULT (mode, out1, GEN_INT (diff & ~1))gen_rtx_fmt_ee_stat ((MULT), ((mode)), ((out1)), ((gen_rtx_CONST_INT
 (((void) 0, E_VOIDmode), (diff & ~1)))) );
     nops++;
     if (diff & 1)
{
  tmp = gen_rtx_PLUS (mode, tmp, out1)gen_rtx_fmt_ee_stat ((PLUS), ((mode)), ((tmp)), ((out1)) );
  nops++;
}
   }
 if (cf != 0)
   {
     tmp = plus_constant (mode, tmp, cf);
     nops++;
   }
 if (!rtx_equal_p (tmp, out))
   {
     if (nops == 1)
out = force_operand (tmp, copy_rtx (out));
     else
emit_insn (gen_rtx_SET (copy_rtx (out), copy_rtx (tmp))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((copy_rtx
 (out))), ((copy_rtx (tmp))) ));
   }
 if (!rtx_equal_p (out, operands[0]))
   emit_move_insn (operands[0], copy_rtx (out));

 return true;
}

    /*
     * General case:			Jumpful:
     *   xorl dest,dest		cmpl op1, op2
     *   cmpl op1, op2		movl ct, dest
     *   setcc dest			jcc 1f
     *   decl dest			movl cf, dest
     *   andl (cf-ct),dest		1:
     *   addl ct,dest
     *
     * Size 20.			Size 14.
     *
     * This is reasonably steep, but branch mispredict costs are
     * high on modern cpus, so consider failing only if optimizing
     * for space.
     */

    if ((!TARGET_CMOVE(ix86_arch_features[X86_ARCH_CMOV] || ((global_options.x_ix86_isa_flags
 & (1UL << 50)) != 0) || ((global_options.x_ix86_isa_flags
 & (1UL << 44)) != 0)) || (mode == QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)) && TARGET_PARTIAL_REG_STALLix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]))
 && BRANCH_COST (optimize_insn_for_speed_p (),(!(optimize_insn_for_speed_p ()) ? 2 : (false) ? 0 : global_options
.x_ix86_branch_cost)
  	  false)(!(optimize_insn_for_speed_p ()) ? 2 : (false) ? 0 : global_options
.x_ix86_branch_cost) >= 2)
{
 if (cf == 0)
   {
     machine_mode cmp_mode = GET_MODE (op0)((machine_mode) (op0)->mode);
     enum rtx_code new_code;

     if (SCALAR_FLOAT_MODE_P (cmp_mode)(((enum mode_class) mode_class[cmp_mode]) == MODE_FLOAT || ((
enum mode_class) mode_class[cmp_mode]) == MODE_DECIMAL_FLOAT))
{
  gcc_assert (!DECIMAL_FLOAT_MODE_P (cmp_mode))((void)(!(!(((enum mode_class) mode_class[cmp_mode]) == MODE_DECIMAL_FLOAT
)) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 3226, __FUNCTION__), 0 : 0));

  /* We may be reversing a non-trapping
     comparison to a trapping comparison.  */
  if (HONOR_NANS (cmp_mode) && flag_trapping_mathglobal_options.x_flag_trapping_math
      && code != EQ && code != NE
      && code != ORDERED && code != UNORDERED)
    new_code = UNKNOWN;
  else
    new_code = reverse_condition_maybe_unordered (code);

}
     else
{
  new_code = ix86_reverse_condition (code, cmp_mode);
  if (compare_code != UNKNOWN && new_code != UNKNOWN)
    compare_code = reverse_condition (compare_code);
}

     if (new_code != UNKNOWN)
{
  cf = ct;
  ct = 0;
  code = new_code;
}
   }

 if (compare_code != UNKNOWN)
   {
     /* notl op1	(if needed)
 sarl $31, op1
 andl (cf-ct), op1
 addl ct, op1

 For x < 0 (resp. x <= -1) there will be no notl,
 so if possible swap the constants to get rid of the
 complement.
 True/false will be -1/0 while code below (store flag
 followed by decrement) is 0/-1, so the constants need
 to be exchanged once more.  */

     if (compare_code == GE || !cf)
{
  code = reverse_condition (code);
  compare_code = LT;
}
     else
std::swap (ct, cf);

     out = emit_store_flag (out, code, op0, op1, VOIDmode((void) 0, E_VOIDmode), 0, -1);
   }
 else
   {
     out = emit_store_flag (out, code, op0, op1, VOIDmode((void) 0, E_VOIDmode), 0, 1);

     out = expand_simple_binop (mode, PLUS, copy_rtx (out),
			 constm1_rtx(const_int_rtx[64 -1]),
			 copy_rtx (out), 1, OPTAB_DIRECT);
   }

 out = expand_simple_binop (mode, AND, copy_rtx (out),
		     gen_int_mode (cf - ct, mode),
		     copy_rtx (out), 1, OPTAB_DIRECT);
 if (ct)
   out = expand_simple_binop (mode, PLUS, copy_rtx (out), GEN_INT (ct)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (ct)),
		       copy_rtx (out), 1, OPTAB_DIRECT);
 if (!rtx_equal_p (out, operands[0]))
   emit_move_insn (operands[0], copy_rtx (out));

 return true;
}
  }

if (!TARGET_CMOVE(ix86_arch_features[X86_ARCH_CMOV] || ((global_options.x_ix86_isa_flags
 & (1UL << 50)) != 0) || ((global_options.x_ix86_isa_flags
 & (1UL << 44)) != 0)) || (mode == QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)) && TARGET_PARTIAL_REG_STALLix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]))
  {
    /* Try a few things more with specific constants and a variable.  */

    optab op;
    rtx var, orig_out, out, tmp;

    if (BRANCH_COST (optimize_insn_for_speed_p (), false)(!(optimize_insn_for_speed_p ()) ? 2 : (false) ? 0 : global_options
.x_ix86_branch_cost) <= 2)
return false;

    /* If one of the two operands is an interesting constant, load a
constant with the above and mask it in with a logical operation.  */

    if (CONST_INT_P (operands[2])(((enum rtx_code) (operands[2])->code) == CONST_INT))
{
 var = operands[3];
 if (INTVAL (operands[2])((operands[2])->u.hwint[0]) == 0 && operands[3] != constm1_rtx(const_int_rtx[64 -1]))
   operands[3] = constm1_rtx(const_int_rtx[64 -1]), op = and_optab;
 else if (INTVAL (operands[2])((operands[2])->u.hwint[0]) == -1 && operands[3] != const0_rtx(const_int_rtx[64]))
   operands[3] = const0_rtx(const_int_rtx[64]), op = ior_optab;
 else
   return false;
}
    else if (CONST_INT_P (operands[3])(((enum rtx_code) (operands[3])->code) == CONST_INT))
{
 var = operands[2];
 if (INTVAL (operands[3])((operands[3])->u.hwint[0]) == 0 && operands[2] != constm1_rtx(const_int_rtx[64 -1]))
   {
     /* For smin (x, 0), expand as "x < 0 ? x : 0" instead of
 "x <= 0 ? x : 0" to enable sign_bit_compare_p.  */
     if (code == LE && op1 == const0_rtx(const_int_rtx[64]) && rtx_equal_p (op0, var))
operands[1] = simplify_gen_relational (LT, VOIDmode((void) 0, E_VOIDmode),
				       GET_MODE (op0)((machine_mode) (op0)->mode),
				       op0, const0_rtx(const_int_rtx[64]));

     operands[2] = constm1_rtx(const_int_rtx[64 -1]);
     op = and_optab;
   }
 else if (INTVAL (operands[3])((operands[3])->u.hwint[0]) == -1 && operands[3] != const0_rtx(const_int_rtx[64]))
   operands[2] = const0_rtx(const_int_rtx[64]), op = ior_optab;
 else
   return false;
}
    else
      return false;

    orig_out = operands[0];
    tmp = gen_reg_rtx (mode);
    operands[0] = tmp;

    /* Recurse to get the constant loaded.  */
    if (!ix86_expand_int_movcc (operands))
      return false;

    /* Mask in the interesting variable.  */
    out = expand_binop (mode, op, var, tmp, orig_out, 0,
	  OPTAB_WIDEN);
    if (!rtx_equal_p (out, orig_out))
emit_move_insn (copy_rtx (orig_out), copy_rtx (out));

    return true;
  }

/*
 * For comparison with above,
 *
 * movl cf,dest
 * movl ct,tmp
 * cmpl op1,op2
 * cmovcc tmp,dest
 *
 * Size 15.
 */

if (! nonimmediate_operand (operands[2], mode))
  operands[2] = force_reg (mode, operands[2]);
if (! nonimmediate_operand (operands[3], mode))
  operands[3] = force_reg (mode, operands[3]);

if (! register_operand (operands[2], VOIDmode((void) 0, E_VOIDmode))
    && (mode == QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode))
        || ! register_operand (operands[3], VOIDmode((void) 0, E_VOIDmode))))
  operands[2] = force_reg (mode, operands[2]);

if (mode == QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode))
    && ! register_operand (operands[3], VOIDmode((void) 0, E_VOIDmode)))
  operands[3] = force_reg (mode, operands[3]);

emit_insn (compare_seq);
emit_insn (gen_rtx_SET (operands[0],gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((operands
[0])), ((gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((mode)), ((compare_op
)), ((operands[2])), ((operands[3])) ))) )
	  gen_rtx_IF_THEN_ELSE (mode,gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((operands
[0])), ((gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((mode)), ((compare_op
)), ((operands[2])), ((operands[3])) ))) )
				compare_op, operands[2],gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((operands
[0])), ((gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((mode)), ((compare_op
)), ((operands[2])), ((operands[3])) ))) )
				operands[3]))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((operands
[0])), ((gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((mode)), ((compare_op
)), ((operands[2])), ((operands[3])) ))) ));
return true;
3393}

3395/* Detect conditional moves that exactly match min/max operational
 semantics.  Note that this is IEEE safe, as long as we don't
 interchange the operands.

 Returns FALSE if this conditional move doesn't match a MIN/MAX,
 and TRUE if the operation is successful and instructions are emitted.  */

3402static bool
3403ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0,
	   rtx cmp_op1, rtx if_true, rtx if_false)
3405{
machine_mode mode;
bool is_min;
rtx tmp;

if (code == LT)
  ;
else if (code == UNGE)
  std::swap (if_true, if_false);
else
  return false;

if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false))
  is_min = true;
else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false))
  is_min = false;
else
  return false;

mode = GET_MODE (dest)((machine_mode) (dest)->mode);

/* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
   but MODE may be a vector mode and thus not appropriate.  */
if (!flag_finite_math_onlyglobal_options.x_flag_finite_math_only || flag_signed_zerosglobal_options.x_flag_signed_zeros)
  {
    int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX;
    rtvec v;

    if_true = force_reg (mode, if_true);
    v = gen_rtvec (2, if_true, if_false);
    tmp = gen_rtx_UNSPEC (mode, v, u)gen_rtx_fmt_Ei_stat ((UNSPEC), ((mode)), ((v)), ((u)) );
  }
else
  {
    code = is_min ? SMIN : SMAX;
    if (MEM_P (if_true)(((enum rtx_code) (if_true)->code) == MEM) && MEM_P (if_false)(((enum rtx_code) (if_false)->code) == MEM))
if_true = force_reg (mode, if_true);
    tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false)gen_rtx_fmt_ee_stat ((code), (mode), (if_true), (if_false) );
  }

emit_insn (gen_rtx_SET (dest, tmp)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((tmp)) ));
return true;
3447}

3449/* Return true if MODE is valid for vector compare to mask register,
 Same result for conditionl vector move with mask register.  */
3451static bool
3452ix86_valid_mask_cmp_mode (machine_mode mode)
3453{
/* XOP has its own vector conditional movement.  */
if (TARGET_XOP((global_options.x_ix86_isa_flags & (1UL << 59)) !=
 0) && !TARGET_AVX512F((global_options.x_ix86_isa_flags & (1UL << 15)) !=
 0))
  return false;

/* AVX512F is needed for mask operation.  */
if (!(TARGET_AVX512F((global_options.x_ix86_isa_flags & (1UL << 15)) !=
 0) && VECTOR_MODE_P (mode)(((enum mode_class) mode_class[mode]) == MODE_VECTOR_BOOL || (
(enum mode_class) mode_class[mode]) == MODE_VECTOR_INT || ((enum
 mode_class) mode_class[mode]) == MODE_VECTOR_FLOAT || ((enum
 mode_class) mode_class[mode]) == MODE_VECTOR_FRACT || ((enum
 mode_class) mode_class[mode]) == MODE_VECTOR_UFRACT || ((enum
 mode_class) mode_class[mode]) == MODE_VECTOR_ACCUM || ((enum
 mode_class) mode_class[mode]) == MODE_VECTOR_UACCUM)))
  return false;

/* AVX512BW is needed for vector QI/HImode,
   AVX512VL is needed for 128/256-bit vector.  */
machine_mode inner_mode = GET_MODE_INNER (mode)(mode_to_inner (mode));
int vector_size = GET_MODE_SIZE (mode)((unsigned short) mode_to_bytes (mode).coeffs[0]);
if ((inner_mode == QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)) || inner_mode == HImode(scalar_int_mode ((scalar_int_mode::from_int) E_HImode))) && !TARGET_AVX512BW((global_options.x_ix86_isa_flags & (1UL << 11)) !=
 0))
  return false;

return vector_size == 64 || TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0);
3470}

3472/* Expand an SSE comparison.  Return the register with the result.  */

3474static rtx
3475ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1,
     rtx op_true, rtx op_false)
3477{
machine_mode mode = GET_MODE (dest)((machine_mode) (dest)->mode);
machine_mode cmp_ops_mode = GET_MODE (cmp_op0)((machine_mode) (cmp_op0)->mode);

/* In general case result of comparison can differ from operands' type.  */
machine_mode cmp_mode;

/* In AVX512F the result of comparison is an integer mask.  */
bool maskcmp = false;
rtx x;

if (ix86_valid_mask_cmp_mode (cmp_ops_mode))
  {
    unsigned int nbits = GET_MODE_NUNITS (cmp_ops_mode)(mode_to_nunits (cmp_ops_mode).coeffs[0]);
    maskcmp = true;
    cmp_mode = nbits > 8 ? int_mode_for_size (nbits, 0).require () : E_QImode;
  }
else
  cmp_mode = cmp_ops_mode;

cmp_op0 = force_reg (cmp_ops_mode, cmp_op0);

int (*op1_predicate)(rtx, machine_mode)
  = VECTOR_MODE_P (cmp_ops_mode)(((enum mode_class) mode_class[cmp_ops_mode]) == MODE_VECTOR_BOOL
 || ((enum mode_class) mode_class[cmp_ops_mode]) == MODE_VECTOR_INT
 || ((enum mode_class) mode_class[cmp_ops_mode]) == MODE_VECTOR_FLOAT
 || ((enum mode_class) mode_class[cmp_ops_mode]) == MODE_VECTOR_FRACT
 || ((enum mode_class) mode_class[cmp_ops_mode]) == MODE_VECTOR_UFRACT
 || ((enum mode_class) mode_class[cmp_ops_mode]) == MODE_VECTOR_ACCUM
 || ((enum mode_class) mode_class[cmp_ops_mode]) == MODE_VECTOR_UACCUM
) ? vector_operand : nonimmediate_operand;

if (!op1_predicate (cmp_op1, cmp_ops_mode))
  cmp_op1 = force_reg (cmp_ops_mode, cmp_op1);

if (optimizeglobal_options.x_optimize
    || (maskcmp && cmp_mode != mode)
    || (op_true && reg_overlap_mentioned_p (dest, op_true))
    || (op_false && reg_overlap_mentioned_p (dest, op_false)))
  dest = gen_reg_rtx (maskcmp ? cmp_mode : mode);

if (maskcmp)
  {
    bool ok = ix86_expand_mask_vec_cmp (dest, code, cmp_op0, cmp_op1);
    gcc_assert (ok)((void)(!(ok) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 3514, __FUNCTION__), 0 : 0));
    return dest;
  }

x = gen_rtx_fmt_ee (code, cmp_mode, cmp_op0, cmp_op1)gen_rtx_fmt_ee_stat ((code), (cmp_mode), (cmp_op0), (cmp_op1)
 );

if (cmp_mode != mode && !maskcmp)
  {
    x = force_reg (cmp_ops_mode, x);
    convert_move (dest, x, false);
  }
else
  emit_insn (gen_rtx_SET (dest, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((x)) ));

return dest;
3529}

3531/* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
 operations.  This is used for both scalar and vector conditional moves.  */

3534void
3535ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false)
3536{
machine_mode mode = GET_MODE (dest)((machine_mode) (dest)->mode);
machine_mode cmpmode = GET_MODE (cmp)((machine_mode) (cmp)->mode);

/* Simplify trivial VEC_COND_EXPR to avoid ICE in pr97506.  */
if (rtx_equal_p (op_true, op_false))
  {
    emit_move_insn (dest, op_true);
    return;
  }

/* In AVX512F the result of comparison is an integer mask.  */
bool maskcmp = mode != cmpmode && ix86_valid_mask_cmp_mode (mode);

rtx t2, t3, x;

/* If we have an integer mask and FP value then we need
   to cast mask to FP mode.  */
if (mode != cmpmode && VECTOR_MODE_P (cmpmode)(((enum mode_class) mode_class[cmpmode]) == MODE_VECTOR_BOOL ||
 ((enum mode_class) mode_class[cmpmode]) == MODE_VECTOR_INT ||
 ((enum mode_class) mode_class[cmpmode]) == MODE_VECTOR_FLOAT
 || ((enum mode_class) mode_class[cmpmode]) == MODE_VECTOR_FRACT
 || ((enum mode_class) mode_class[cmpmode]) == MODE_VECTOR_UFRACT
 || ((enum mode_class) mode_class[cmpmode]) == MODE_VECTOR_ACCUM
 || ((enum mode_class) mode_class[cmpmode]) == MODE_VECTOR_UACCUM
))
  {
    cmp = force_reg (cmpmode, cmp);
    cmp = gen_rtx_SUBREG (mode, cmp, 0);
  }

if (maskcmp)
  {
    /* Using vector move with mask register.  */
    cmp = force_reg (cmpmode, cmp);
    /* Optimize for mask zero.  */
    op_true = (op_true != CONST0_RTX (mode)(const_tiny_rtx[0][(int) (mode)])
 ? force_reg (mode, op_true) : op_true);
    op_false = (op_false != CONST0_RTX (mode)(const_tiny_rtx[0][(int) (mode)])
  ? force_reg (mode, op_false) : op_false);
    if (op_true == CONST0_RTX (mode)(const_tiny_rtx[0][(int) (mode)]))
{
 rtx (*gen_not) (rtx, rtx);
 switch (cmpmode)
   {
   case E_QImode: gen_not = gen_knotqi; break;
   case E_HImode: gen_not = gen_knothi; break;
   case E_SImode: gen_not = gen_knotsi; break;
   case E_DImode: gen_not = gen_knotdi; break;
   default: gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 3578, __FUNCTION__));
   }
 rtx n = gen_reg_rtx (cmpmode);
 emit_insn (gen_not (n, cmp));
 cmp = n;
 /* Reverse op_true op_false.  */
 std::swap (op_true, op_false);
}

    rtx vec_merge = gen_rtx_VEC_MERGE (mode, op_true, op_false, cmp)gen_rtx_fmt_eee_stat ((VEC_MERGE), ((mode)), ((op_true)), ((op_false
)), ((cmp)) );
    emit_insn (gen_rtx_SET (dest, vec_merge)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((vec_merge)) ));
    return;
  }
else if (vector_all_ones_operand (op_true, mode)
  && op_false == CONST0_RTX (mode)(const_tiny_rtx[0][(int) (mode)]))
  {
    emit_insn (gen_rtx_SET (dest, cmp)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((cmp)) ));
    return;
  }
else if (op_false == CONST0_RTX (mode)(const_tiny_rtx[0][(int) (mode)]))
  {
    op_true = force_reg (mode, op_true);
    x = gen_rtx_AND (mode, cmp, op_true)gen_rtx_fmt_ee_stat ((AND), ((mode)), ((cmp)), ((op_true)) );
    emit_insn (gen_rtx_SET (dest, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((x)) ));
    return;
  }
else if (op_true == CONST0_RTX (mode)(const_tiny_rtx[0][(int) (mode)]))
  {
    op_false = force_reg (mode, op_false);
    x = gen_rtx_NOT (mode, cmp)gen_rtx_fmt_e_stat ((NOT), ((mode)), ((cmp)) );
    x = gen_rtx_AND (mode, x, op_false)gen_rtx_fmt_ee_stat ((AND), ((mode)), ((x)), ((op_false)) );
    emit_insn (gen_rtx_SET (dest, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((x)) ));
    return;
  }
else if (INTEGRAL_MODE_P (mode)(((enum mode_class) mode_class[mode]) == MODE_INT || ((enum mode_class
) mode_class[mode]) == MODE_PARTIAL_INT || ((enum mode_class)
 mode_class[mode]) == MODE_COMPLEX_INT || ((enum mode_class) mode_class
[mode]) == MODE_VECTOR_BOOL || ((enum mode_class) mode_class[
mode]) == MODE_VECTOR_INT) && op_true == CONSTM1_RTX (mode)(const_tiny_rtx[3][(int) (mode)]))
  {
    op_false = force_reg (mode, op_false);
    x = gen_rtx_IOR (mode, cmp, op_false)gen_rtx_fmt_ee_stat ((IOR), ((mode)), ((cmp)), ((op_false)) );
    emit_insn (gen_rtx_SET (dest, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((x)) ));
    return;
  }
else if (TARGET_XOP((global_options.x_ix86_isa_flags & (1UL << 59)) !=
 0))
  {
    op_true = force_reg (mode, op_true);

    if (!nonimmediate_operand (op_false, mode))
op_false = force_reg (mode, op_false);

    emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (mode, cmp,gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((mode)), ((cmp)),
 ((op_true)), ((op_false)) ))) )
					  op_true,gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((mode)), ((cmp)),
 ((op_true)), ((op_false)) ))) )
					  op_false))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((mode)), ((cmp)),
 ((op_true)), ((op_false)) ))) ));
    return;
  }

rtx (*gen) (rtx, rtx, rtx, rtx) = NULL__null;
rtx d = dest;

if (!vector_operand (op_true, mode))
  op_true = force_reg (mode, op_true);

op_false = force_reg (mode, op_false);

switch (mode)
  {
  case E_V4SFmode:
    if (TARGET_SSE4_1((global_options.x_ix86_isa_flags & (1UL << 38)) !=
 0))
gen = gen_sse4_1_blendvps;
    break;
  case E_V2DFmode:
    if (TARGET_SSE4_1((global_options.x_ix86_isa_flags & (1UL << 38)) !=
 0))
gen = gen_sse4_1_blendvpd;
    break;
  case E_SFmode:
    if (TARGET_SSE4_1((global_options.x_ix86_isa_flags & (1UL << 38)) !=
 0))
{
 gen = gen_sse4_1_blendvss;
 op_true = force_reg (mode, op_true);
}
    break;
  case E_DFmode:
    if (TARGET_SSE4_1((global_options.x_ix86_isa_flags & (1UL << 38)) !=
 0))
{
 gen = gen_sse4_1_blendvsd;
 op_true = force_reg (mode, op_true);
}
    break;
  case E_V16QImode:
  case E_V8HImode:
  case E_V4SImode:
  case E_V2DImode:
    if (TARGET_SSE4_1((global_options.x_ix86_isa_flags & (1UL << 38)) !=
 0))
{
 gen = gen_sse4_1_pblendvb;
 if (mode != V16QImode((void) 0, E_V16QImode))
   d = gen_reg_rtx (V16QImode((void) 0, E_V16QImode));
 op_false = gen_lowpartrtl_hooks.gen_lowpart (V16QImode((void) 0, E_V16QImode), op_false);
 op_true = gen_lowpartrtl_hooks.gen_lowpart (V16QImode((void) 0, E_V16QImode), op_true);
 cmp = gen_lowpartrtl_hooks.gen_lowpart (V16QImode((void) 0, E_V16QImode), cmp);
}
    break;
  case E_V8SFmode:
    if (TARGET_AVX((global_options.x_ix86_isa_flags & (1UL << 8)) != 0
))
gen = gen_avx_blendvps256;
    break;
  case E_V4DFmode:
    if (TARGET_AVX((global_options.x_ix86_isa_flags & (1UL << 8)) != 0
))
gen = gen_avx_blendvpd256;
    break;
  case E_V32QImode:
  case E_V16HImode:
  case E_V8SImode:
  case E_V4DImode:
    if (TARGET_AVX2((global_options.x_ix86_isa_flags & (1UL << 9)) != 0
))
{
 gen = gen_avx2_pblendvb;
 if (mode != V32QImode((void) 0, E_V32QImode))
   d = gen_reg_rtx (V32QImode((void) 0, E_V32QImode));
 op_false = gen_lowpartrtl_hooks.gen_lowpart (V32QImode((void) 0, E_V32QImode), op_false);
 op_true = gen_lowpartrtl_hooks.gen_lowpart (V32QImode((void) 0, E_V32QImode), op_true);
 cmp = gen_lowpartrtl_hooks.gen_lowpart (V32QImode((void) 0, E_V32QImode), cmp);
}
    break;

  case E_V64QImode:
    gen = gen_avx512bw_blendmv64qi;
    break;
  case E_V32HImode:
    gen = gen_avx512bw_blendmv32hi;
    break;
  case E_V16SImode:
    gen = gen_avx512f_blendmv16si;
    break;
  case E_V8DImode:
    gen = gen_avx512f_blendmv8di;
    break;
  case E_V8DFmode:
    gen = gen_avx512f_blendmv8df;
    break;
  case E_V16SFmode:
    gen = gen_avx512f_blendmv16sf;
    break;

  default:
    break;
  }

if (gen != NULL__null)
  {
    emit_insn (gen (d, op_false, op_true, cmp));
    if (d != dest)
emit_move_insn (dest, gen_lowpartrtl_hooks.gen_lowpart (GET_MODE (dest)((machine_mode) (dest)->mode), d));
  }
else
  {
    op_true = force_reg (mode, op_true);

    t2 = gen_reg_rtx (mode);
    if (optimizeglobal_options.x_optimize)
t3 = gen_reg_rtx (mode);
    else
t3 = dest;

    x = gen_rtx_AND (mode, op_true, cmp)gen_rtx_fmt_ee_stat ((AND), ((mode)), ((op_true)), ((cmp)) );
    emit_insn (gen_rtx_SET (t2, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((t2)),
 ((x)) ));

    x = gen_rtx_NOT (mode, cmp)gen_rtx_fmt_e_stat ((NOT), ((mode)), ((cmp)) );
    x = gen_rtx_AND (mode, x, op_false)gen_rtx_fmt_ee_stat ((AND), ((mode)), ((x)), ((op_false)) );
    emit_insn (gen_rtx_SET (t3, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((t3)),
 ((x)) ));

    x = gen_rtx_IOR (mode, t3, t2)gen_rtx_fmt_ee_stat ((IOR), ((mode)), ((t3)), ((t2)) );
    emit_insn (gen_rtx_SET (dest, x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((x)) ));
  }
3750}

3752/* Swap, force into registers, or otherwise massage the two operands
 to an sse comparison with a mask result.  Thus we differ a bit from
 ix86_prepare_fp_compare_args which expects to produce a flags result.

 The DEST operand exists to help determine whether to commute commutative
 operators.  The POP0/POP1 operands are updated in place.  The new
 comparison code is returned, or UNKNOWN if not implementable.  */

3760static enum rtx_code
3761ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code,
		  rtx *pop0, rtx *pop1)
3763{
switch (code)
  {
  case LTGT:
  case UNEQ:
    /* AVX supports all the needed comparisons.  */
    if (TARGET_AVX((global_options.x_ix86_isa_flags & (1UL << 8)) != 0
))
break;
    /* We have no LTGT as an operator.  We could implement it with
NE & ORDERED, but this requires an extra temporary.  It's
not clear that it's worth it.  */
    return UNKNOWN;

  case LT:
  case LE:
  case UNGT:
  case UNGE:
    /* These are supported directly.  */
    break;

  case EQ:
  case NE:
  case UNORDERED:
  case ORDERED:
    /* AVX has 3 operand comparisons, no need to swap anything.  */
    if (TARGET_AVX((global_options.x_ix86_isa_flags & (1UL << 8)) != 0
))
break;
    /* For commutative operators, try to canonicalize the destination
operand to be first in the comparison - this helps reload to
avoid extra moves.  */
    if (!dest || !rtx_equal_p (dest, *pop1))
break;
    /* FALLTHRU */

  case GE:
  case GT:
  case UNLE:
  case UNLT:
    /* These are not supported directly before AVX, and furthermore
ix86_expand_sse_fp_minmax only optimizes LT/UNGE.  Swap the
comparison operands to transform into something that is
supported.  */
    std::swap (*pop0, *pop1);
    code = swap_condition (code);
    break;

  default:
    gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 3810, __FUNCTION__));
  }

return code;
3814}

3816/* Expand a floating-point conditional move.  Return true if successful.  */

3818bool
3819ix86_expand_fp_movcc (rtx operands[])
3820{
machine_mode mode = GET_MODE (operands[0])((machine_mode) (operands[0])->mode);
enum rtx_code code = GET_CODE (operands[1])((enum rtx_code) (operands[1])->code);
rtx tmp, compare_op;
rtx op0 = XEXP (operands[1], 0)(((operands[1])->u.fld[0]).rt_rtx);
rtx op1 = XEXP (operands[1], 1)(((operands[1])->u.fld[1]).rt_rtx);

if (TARGET_SSE_MATH((global_options.x_ix86_fpmath & FPMATH_SSE) != 0) && SSE_FLOAT_MODE_P (mode)((((global_options.x_ix86_isa_flags & (1UL << 50)) !=
 0) && (mode) == (scalar_float_mode ((scalar_float_mode
::from_int) E_SFmode))) || (((global_options.x_ix86_isa_flags
 & (1UL << 51)) != 0) && (mode) == (scalar_float_mode
 ((scalar_float_mode::from_int) E_DFmode)))))
  {
    machine_mode cmode;

    /* Since we've no cmove for sse registers, don't force bad register
allocation just to gain access to it.  Deny movcc when the
comparison mode doesn't match the move mode.  */
    cmode = GET_MODE (op0)((machine_mode) (op0)->mode);
    if (cmode == VOIDmode((void) 0, E_VOIDmode))
cmode = GET_MODE (op1)((machine_mode) (op1)->mode);
    if (cmode != mode)
return false;

    code = ix86_prepare_sse_fp_compare_args (operands[0], code, &op0, &op1);
    if (code == UNKNOWN)
return false;

    if (ix86_expand_sse_fp_minmax (operands[0], code, op0, op1,
		     operands[2], operands[3]))
return true;

    tmp = ix86_expand_sse_cmp (operands[0], code, op0, op1,
		 operands[2], operands[3]);
    ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]);
    return true;
  }

if (GET_MODE (op0)((machine_mode) (op0)->mode) == TImode(scalar_int_mode ((scalar_int_mode::from_int) E_TImode))
    || (GET_MODE (op0)((machine_mode) (op0)->mode) == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode))
 && !TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
)))
  return false;

/* The floating point conditional move instructions don't directly
   support conditions resulting from a signed integer comparison.  */

compare_op = ix86_expand_compare (code, op0, op1);
if (!fcmov_comparison_operator (compare_op, VOIDmode((void) 0, E_VOIDmode)))
  {
    tmp = gen_reg_rtx (QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)));
    ix86_expand_setcc (tmp, code, op0, op1);

    compare_op = ix86_expand_compare (NE, tmp, const0_rtx(const_int_rtx[64]));
  }

emit_insn (gen_rtx_SET (operands[0],gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((operands
[0])), ((gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((mode)), ((compare_op
)), ((operands[2])), ((operands[3])) ))) )
	  gen_rtx_IF_THEN_ELSE (mode, compare_op,gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((operands
[0])), ((gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((mode)), ((compare_op
)), ((operands[2])), ((operands[3])) ))) )
				operands[2], operands[3]))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((operands
[0])), ((gen_rtx_fmt_eee_stat ((IF_THEN_ELSE), ((mode)), ((compare_op
)), ((operands[2])), ((operands[3])) ))) ));

return true;
3876}

3878/* Helper for ix86_cmp_code_to_pcmp_immediate for int modes.  */

3880static int
3881ix86_int_cmp_code_to_pcmp_immediate (enum rtx_code code)
3882{
switch (code)
  {
  case EQ:
    return 0;
  case LT:
  case LTU:
    return 1;
  case LE:
  case LEU:
    return 2;
  case NE:
    return 4;
  case GE:
  case GEU:
    return 5;
  case GT:
  case GTU:
    return 6;
  default:
    gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 3902, __FUNCTION__));
  }
3904}

3906/* Helper for ix86_cmp_code_to_pcmp_immediate for fp modes.  */

3908static int
3909ix86_fp_cmp_code_to_pcmp_immediate (enum rtx_code code)
3910{
switch (code)
  {
  case EQ:
    return 0x00;
  case NE:
    return 0x04;
  case GT:
    return 0x0e;
  case LE:
    return 0x02;
  case GE:
    return 0x0d;
  case LT:
    return 0x01;
  case UNLE:
    return 0x0a;
  case UNLT:
    return 0x09;
  case UNGE:
    return 0x05;
  case UNGT:
    return 0x06;
  case UNEQ:
    return 0x18;
  case LTGT:
    return 0x0c;
  case ORDERED:
    return 0x07;
  case UNORDERED:
    return 0x03;
  default:
    gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 3942, __FUNCTION__));
  }
3944}

3946/* Return immediate value to be used in UNSPEC_PCMP
 for comparison CODE in MODE.  */

3949static int
3950ix86_cmp_code_to_pcmp_immediate (enum rtx_code code, machine_mode mode)
3951{
if (FLOAT_MODE_P (mode)(((enum mode_class) mode_class[mode]) == MODE_FLOAT || ((enum
 mode_class) mode_class[mode]) == MODE_DECIMAL_FLOAT || ((enum
 mode_class) mode_class[mode]) == MODE_COMPLEX_FLOAT || ((enum
 mode_class) mode_class[mode]) == MODE_VECTOR_FLOAT))
  return ix86_fp_cmp_code_to_pcmp_immediate (code);
return ix86_int_cmp_code_to_pcmp_immediate (code);
3955}

3957/* Expand AVX-512 vector comparison.  */

3959bool
3960ix86_expand_mask_vec_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1)
3961{
machine_mode mask_mode = GET_MODE (dest)((machine_mode) (dest)->mode);
machine_mode cmp_mode = GET_MODE (cmp_op0)((machine_mode) (cmp_op0)->mode);
rtx imm = GEN_INT (ix86_cmp_code_to_pcmp_immediate (code, cmp_mode))gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (ix86_cmp_code_to_pcmp_immediate
 (code, cmp_mode)));
int unspec_code;
rtx unspec;

switch (code)
  {
  case LEU:
  case GTU:
  case GEU:
  case LTU:
    unspec_code = UNSPEC_UNSIGNED_PCMP;
    break;

  default:
    unspec_code = UNSPEC_PCMP;
  }

unspec = gen_rtx_UNSPEC (mask_mode, gen_rtvec (3, cmp_op0, cmp_op1, imm),gen_rtx_fmt_Ei_stat ((UNSPEC), ((mask_mode)), ((gen_rtvec (3,
 cmp_op0, cmp_op1, imm))), ((unspec_code)) )
	   unspec_code)gen_rtx_fmt_Ei_stat ((UNSPEC), ((mask_mode)), ((gen_rtvec (3,
 cmp_op0, cmp_op1, imm))), ((unspec_code)) );
emit_insn (gen_rtx_SET (dest, unspec)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((dest)
), ((unspec)) ));

return true;
3986}

3988/* Expand fp vector comparison.  */

3990bool
3991ix86_expand_fp_vec_cmp (rtx operands[])
3992{
enum rtx_code code = GET_CODE (operands[1])((enum rtx_code) (operands[1])->code);
rtx cmp;

code = ix86_prepare_sse_fp_compare_args (operands[0], code,
			   &operands[2], &operands[3]);
if (code == UNKNOWN)
  {
    rtx temp;
    switch (GET_CODE (operands[1])((enum rtx_code) (operands[1])->code))
{
case LTGT:
 temp = ix86_expand_sse_cmp (operands[0], ORDERED, operands[2],
		      operands[3], NULL__null, NULL__null);
 cmp = ix86_expand_sse_cmp (operands[0], NE, operands[2],
		     operands[3], NULL__null, NULL__null);
 code = AND;
 break;
case UNEQ:
 temp = ix86_expand_sse_cmp (operands[0], UNORDERED, operands[2],
		      operands[3], NULL__null, NULL__null);
 cmp = ix86_expand_sse_cmp (operands[0], EQ, operands[2],
		     operands[3], NULL__null, NULL__null);
 code = IOR;
 break;
default:
 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 4018, __FUNCTION__));
}
    cmp = expand_simple_binop (GET_MODE (cmp)((machine_mode) (cmp)->mode), code, temp, cmp, cmp, 1,
		 OPTAB_DIRECT);
  }
else
  cmp = ix86_expand_sse_cmp (operands[0], code, operands[2], operands[3],
	       operands[1], operands[2]);

if (operands[0] != cmp)
  emit_move_insn (operands[0], cmp);

return true;
4031}

4033static rtx
4034ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1,
	 rtx op_true, rtx op_false, bool *negate)
4036{
machine_mode data_mode = GET_MODE (dest)((machine_mode) (dest)->mode);
machine_mode mode = GET_MODE (cop0)((machine_mode) (cop0)->mode);
rtx x;

*negate = false;

/* XOP supports all of the comparisons on all 128-bit vector int types.  */
if (TARGET_XOP((global_options.x_ix86_isa_flags & (1UL << 59)) !=
 0)
    && (mode == V16QImode((void) 0, E_V16QImode) || mode == V8HImode((void) 0, E_V8HImode)
 || mode == V4SImode((void) 0, E_V4SImode) || mode == V2DImode((void) 0, E_V2DImode)))
  ;
/* AVX512F supports all of the comparsions
   on all 128/256/512-bit vector int types.  */
else if (ix86_valid_mask_cmp_mode (mode))
  ;
else
  {
    /* Canonicalize the comparison to EQ, GT, GTU.  */
    switch (code)
{
case EQ:
case GT:
case GTU:
 break;

case NE:
case LE:
case LEU:
 code = reverse_condition (code);
 *negate = true;
 break;

case GE:
case GEU:
 code = reverse_condition (code);
 *negate = true;
 /* FALLTHRU */

case LT:
case LTU:
 std::swap (cop0, cop1);
 code = swap_condition (code);
 break;

default:
 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 4082, __FUNCTION__));
}

    /* Only SSE4.1/SSE4.2 supports V2DImode.  */
    if (mode == V2DImode((void) 0, E_V2DImode))
{
 switch (code)
   {
   case EQ:
     /* SSE4.1 supports EQ.  */
     if (!TARGET_SSE4_1((global_options.x_ix86_isa_flags & (1UL << 38)) !=
 0))
return NULL__null;
     break;

   case GT:
   case GTU:
     /* SSE4.2 supports GT/GTU.  */
     if (!TARGET_SSE4_2((global_options.x_ix86_isa_flags & (1UL << 53)) !=
 0))
return NULL__null;
     break;

   default:
     gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 4104, __FUNCTION__));
   }
}

    rtx optrue = op_true ? op_true : CONSTM1_RTX (data_mode)(const_tiny_rtx[3][(int) (data_mode)]);
    rtx opfalse = op_false ? op_false : CONST0_RTX (data_mode)(const_tiny_rtx[0][(int) (data_mode)]);
    if (*negate)
std::swap (optrue, opfalse);

    /* Transform x > y ? 0 : -1 (i.e. x <= y ? -1 : 0 or x <= y) when
not using integer masks into min (x, y) == x ? -1 : 0 (i.e.
min (x, y) == x).  While we add one instruction (the minimum),
we remove the need for two instructions in the negation, as the
result is done this way.
When using masks, do it for SI/DImode element types, as it is shorter
than the two subtractions.  */
    if ((code != EQ
  && GET_MODE_SIZE (mode)((unsigned short) mode_to_bytes (mode).coeffs[0]) != 64
  && vector_all_ones_operand (opfalse, data_mode)
  && optrue == CONST0_RTX (data_mode)(const_tiny_rtx[0][(int) (data_mode)]))
 || (code == GTU
     && GET_MODE_SIZE (GET_MODE_INNER (mode))((unsigned short) mode_to_bytes ((mode_to_inner (mode))).coeffs
[0]) >= 4
     /* Don't do it if not using integer masks and we'd end up with
 the right values in the registers though.  */
     && (GET_MODE_SIZE (mode)((unsigned short) mode_to_bytes (mode).coeffs[0]) == 64
  || !vector_all_ones_operand (optrue, data_mode)
  || opfalse != CONST0_RTX (data_mode)(const_tiny_rtx[0][(int) (data_mode)]))))
{
 rtx (*gen) (rtx, rtx, rtx) = NULL__null;

 switch (mode)
   {
   case E_V16SImode:
     gen = (code == GTU) ? gen_uminv16si3 : gen_sminv16si3;
     break;
   case E_V8DImode:
     gen = (code == GTU) ? gen_uminv8di3 : gen_sminv8di3;
     cop0 = force_reg (mode, cop0);
     cop1 = force_reg (mode, cop1);
     break;
   case E_V32QImode:
     if (TARGET_AVX2((global_options.x_ix86_isa_flags & (1UL << 9)) != 0
))
gen = (code == GTU) ? gen_uminv32qi3 : gen_sminv32qi3;
     break;
   case E_V16HImode:
     if (TARGET_AVX2((global_options.x_ix86_isa_flags & (1UL << 9)) != 0
))
gen = (code == GTU) ? gen_uminv16hi3 : gen_sminv16hi3;
     break;
   case E_V8SImode:
     if (TARGET_AVX2((global_options.x_ix86_isa_flags & (1UL << 9)) != 0
))
gen = (code == GTU) ? gen_uminv8si3 : gen_sminv8si3;
     break;
   case E_V4DImode:
     if (TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0))
{
  gen = (code == GTU) ? gen_uminv4di3 : gen_sminv4di3;
  cop0 = force_reg (mode, cop0);
  cop1 = force_reg (mode, cop1);
}
     break;
   case E_V16QImode:
     if (code == GTU && TARGET_SSE2((global_options.x_ix86_isa_flags & (1UL << 51)) !=
 0))
gen = gen_uminv16qi3;
     else if (code == GT && TARGET_SSE4_1((global_options.x_ix86_isa_flags & (1UL << 38)) !=
 0))
gen = gen_sminv16qi3;
     break;
   case E_V8HImode:
     if (code == GTU && TARGET_SSE4_1((global_options.x_ix86_isa_flags & (1UL << 38)) !=
 0))
gen = gen_uminv8hi3;
     else if (code == GT && TARGET_SSE2((global_options.x_ix86_isa_flags & (1UL << 51)) !=
 0))
gen = gen_sminv8hi3;
     break;
   case E_V4SImode:
     if (TARGET_SSE4_1((global_options.x_ix86_isa_flags & (1UL << 38)) !=
 0))
gen = (code == GTU) ? gen_uminv4si3 : gen_sminv4si3;
     break;
   case E_V2DImode:
     if (TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0))
{
  gen = (code == GTU) ? gen_uminv2di3 : gen_sminv2di3;
  cop0 = force_reg (mode, cop0);
  cop1 = force_reg (mode, cop1);
}
     break;
   default:
     break;
   }

 if (gen)
   {
     rtx tem = gen_reg_rtx (mode);
     if (!vector_operand (cop0, mode))
cop0 = force_reg (mode, cop0);
     if (!vector_operand (cop1, mode))
cop1 = force_reg (mode, cop1);
     *negate = !*negate;
     emit_insn (gen (tem, cop0, cop1));
     cop1 = tem;
     code = EQ;
   }
}

    /* Unsigned parallel compare is not supported by the hardware.
Play some tricks to turn this into a signed comparison
against 0.  */
    if (code == GTU)
{
 cop0 = force_reg (mode, cop0);

 switch (mode)
   {
   case E_V16SImode:
   case E_V8DImode:
   case E_V8SImode:
   case E_V4DImode:
   case E_V4SImode:
   case E_V2DImode:
{
  rtx t1, t2, mask;

  /* Subtract (-(INT MAX) - 1) from both operands to make
     them signed.  */
  mask = ix86_build_signbit_mask (mode, true, false);
  t1 = gen_reg_rtx (mode);
  emit_insn (gen_sub3_insn (t1, cop0, mask));

  t2 = gen_reg_rtx (mode);
  emit_insn (gen_sub3_insn (t2, cop1, mask));

  cop0 = t1;
  cop1 = t2;
  code = GT;
}
     break;

   case E_V64QImode:
   case E_V32HImode:
   case E_V32QImode:
   case E_V16HImode:
   case E_V16QImode:
   case E_V8HImode:
     /* Perform a parallel unsigned saturating subtraction.  */
     x = gen_reg_rtx (mode);
     emit_insn (gen_rtx_SETgen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((x)), (
(gen_rtx_fmt_ee_stat ((US_MINUS), ((mode)), ((cop0)), ((cop1)
) ))) )
	 (x, gen_rtx_US_MINUS (mode, cop0, cop1))gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((x)), (
(gen_rtx_fmt_ee_stat ((US_MINUS), ((mode)), ((cop0)), ((cop1)
) ))) ));
     cop0 = x;
     cop1 = CONST0_RTX (mode)(const_tiny_rtx[0][(int) (mode)]);
     code = EQ;
     *negate = !*negate;
     break;

   default:
     gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 4256, __FUNCTION__));
   }
}
  }

if (*negate)
  std::swap (op_true, op_false);

/* Allow the comparison to be done in one mode, but the movcc to
   happen in another mode.  */
if (data_mode == mode)
  {
    x = ix86_expand_sse_cmp (dest, code, cop0, cop1,
	       op_true, op_false);
  }
else
  {
    gcc_assert (GET_MODE_SIZE (data_mode) == GET_MODE_SIZE (mode))((void)(!(((unsigned short) mode_to_bytes (data_mode).coeffs[
0]) == ((unsigned short) mode_to_bytes (mode).coeffs[0])) ? fancy_abort
 ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 4273, __FUNCTION__), 0 : 0));
    x = ix86_expand_sse_cmp (gen_reg_rtx (mode), code, cop0, cop1,
	       op_true, op_false);
    if (GET_MODE (x)((machine_mode) (x)->mode) == mode)
x = gen_lowpartrtl_hooks.gen_lowpart (data_mode, x);
  }

return x;
4281}

4283/* Expand integer vector comparison.  */

4285bool
4286ix86_expand_int_vec_cmp (rtx operands[])
4287{
rtx_code code = GET_CODE (operands[1])((enum rtx_code) (operands[1])->code);
bool negate = false;
rtx cmp = ix86_expand_int_sse_cmp (operands[0], code, operands[2],
		     operands[3], NULL__null, NULL__null, &negate);

if (!cmp)
  return false;

if (negate)
  cmp = ix86_expand_int_sse_cmp (operands[0], EQ, cmp,
		   CONST0_RTX (GET_MODE (cmp))(const_tiny_rtx[0][(int) (((machine_mode) (cmp)->mode))]),
		   NULL__null, NULL__null, &negate);

gcc_assert (!negate)((void)(!(!negate) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 4301, __FUNCTION__), 0 : 0));

if (operands[0] != cmp)
  emit_move_insn (operands[0], cmp);

return true;
4307}

4309/* Expand a floating-point vector conditional move; a vcond operation
 rather than a movcc operation.  */

4312bool
4313ix86_expand_fp_vcond (rtx operands[])
4314{
enum rtx_code code = GET_CODE (operands[3])((enum rtx_code) (operands[3])->code);
rtx cmp;

code = ix86_prepare_sse_fp_compare_args (operands[0], code,
			   &operands[4], &operands[5]);
if (code == UNKNOWN)
  {
    rtx temp;
    switch (GET_CODE (operands[3])((enum rtx_code) (operands[3])->code))
{
case LTGT:
 temp = ix86_expand_sse_cmp (operands[0], ORDERED, operands[4],
		      operands[5], operands[0], operands[0]);
 cmp = ix86_expand_sse_cmp (operands[0], NE, operands[4],
		     operands[5], operands[1], operands[2]);
 code = AND;
 break;
case UNEQ:
 temp = ix86_expand_sse_cmp (operands[0], UNORDERED, operands[4],
		      operands[5], operands[0], operands[0]);
 cmp = ix86_expand_sse_cmp (operands[0], EQ, operands[4],
		     operands[5], operands[1], operands[2]);
 code = IOR;
 break;
default:
 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 4340, __FUNCTION__));
}
    cmp = expand_simple_binop (GET_MODE (cmp)((machine_mode) (cmp)->mode), code, temp, cmp, cmp, 1,
		 OPTAB_DIRECT);
    ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
    return true;
  }

if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4],
		 operands[5], operands[1], operands[2]))
  return true;

cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5],
	     operands[1], operands[2]);
ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]);
return true;
4356}

4358/* Expand a signed/unsigned integral vector conditional move.  */

4360bool
4361ix86_expand_int_vcond (rtx operands[])
4362{
machine_mode data_mode = GET_MODE (operands[0])((machine_mode) (operands[0])->mode);
machine_mode mode = GET_MODE (operands[4])((machine_mode) (operands[4])->mode);
enum rtx_code code = GET_CODE (operands[3])((enum rtx_code) (operands[3])->code);
bool negate = false;
rtx x, cop0, cop1;

cop0 = operands[4];
cop1 = operands[5];

/* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
   and x < 0 ? 1 : 0 into (unsigned) x >> 31.  */
if ((code == LT || code == GE)
    && data_mode == mode
    && cop1 == CONST0_RTX (mode)(const_tiny_rtx[0][(int) (mode)])
    && operands[1 + (code == LT)] == CONST0_RTX (data_mode)(const_tiny_rtx[0][(int) (data_mode)])
    && GET_MODE_UNIT_SIZE (data_mode)mode_to_unit_size (data_mode) > 1
    && GET_MODE_UNIT_SIZE (data_mode)mode_to_unit_size (data_mode) <= 8
    && (GET_MODE_SIZE (data_mode)((unsigned short) mode_to_bytes (data_mode).coeffs[0]) == 16
 || (TARGET_AVX2((global_options.x_ix86_isa_flags & (1UL << 9)) != 0
) && GET_MODE_SIZE (data_mode)((unsigned short) mode_to_bytes (data_mode).coeffs[0]) == 32)))
  {
    rtx negop = operands[2 - (code == LT)];
    int shift = GET_MODE_UNIT_BITSIZE (data_mode)((unsigned short) (mode_to_unit_size (data_mode) * (8))) - 1;
    if (negop == CONST1_RTX (data_mode)(const_tiny_rtx[1][(int) (data_mode)]))
{
 rtx res = expand_simple_binop (mode, LSHIFTRT, cop0, GEN_INT (shift)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (shift)),
			 operands[0], 1, OPTAB_DIRECT);
 if (res != operands[0])
   emit_move_insn (operands[0], res);
 return true;
}
    else if (GET_MODE_INNER (data_mode)(mode_to_inner (data_mode)) != DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode))
      && vector_all_ones_operand (negop, data_mode))
{
 rtx res = expand_simple_binop (mode, ASHIFTRT, cop0, GEN_INT (shift)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (shift)),
			 operands[0], 0, OPTAB_DIRECT);
 if (res != operands[0])
   emit_move_insn (operands[0], res);
 return true;
}
  }

if (!nonimmediate_operand (cop1, mode))
  cop1 = force_reg (mode, cop1);
if (!general_operand (operands[1], data_mode))
  operands[1] = force_reg (data_mode, operands[1]);
if (!general_operand (operands[2], data_mode))
  operands[2] = force_reg (data_mode, operands[2]);

x = ix86_expand_int_sse_cmp (operands[0], code, cop0, cop1,
	       operands[1], operands[2], &negate);

if (!x)
  return false;

ix86_expand_sse_movcc (operands[0], x, operands[1+negate],
	 operands[2-negate]);
return true;
4420}

4422static bool
4423ix86_expand_vec_perm_vpermt2 (rtx target, rtx mask, rtx op0, rtx op1,
	      struct expand_vec_perm_d *d)
4425{
/* ix86_expand_vec_perm_vpermt2 is called from both const and non-const
   expander, so args are either in d, or in op0, op1 etc.  */
machine_mode mode = GET_MODE (d ? d->op0 : op0)((machine_mode) (d ? d->op0 : op0)->mode);
machine_mode maskmode = mode;
rtx (*gen) (rtx, rtx, rtx, rtx) = NULL__null;

switch (mode)
  {
  case E_V8HImode:
    if (TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0) && TARGET_AVX512BW((global_options.x_ix86_isa_flags & (1UL << 11)) !=
 0))
gen = gen_avx512vl_vpermt2varv8hi3;
    break;
  case E_V16HImode:
    if (TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0) && TARGET_AVX512BW((global_options.x_ix86_isa_flags & (1UL << 11)) !=
 0))
gen = gen_avx512vl_vpermt2varv16hi3;
    break;
  case E_V64QImode:
    if (TARGET_AVX512VBMI((global_options.x_ix86_isa_flags & (1UL << 18)) !=
 0))
gen = gen_avx512bw_vpermt2varv64qi3;
    break;
  case E_V32HImode:
    if (TARGET_AVX512BW((global_options.x_ix86_isa_flags & (1UL << 11)) !=
 0))
gen = gen_avx512bw_vpermt2varv32hi3;
    break;
  case E_V4SImode:
    if (TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0))
gen = gen_avx512vl_vpermt2varv4si3;
    break;
  case E_V8SImode:
    if (TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0))
gen = gen_avx512vl_vpermt2varv8si3;
    break;
  case E_V16SImode:
    if (TARGET_AVX512F((global_options.x_ix86_isa_flags & (1UL << 15)) !=
 0))
gen = gen_avx512f_vpermt2varv16si3;
    break;
  case E_V4SFmode:
    if (TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0))
{
 gen = gen_avx512vl_vpermt2varv4sf3;
 maskmode = V4SImode((void) 0, E_V4SImode);
}
    break;
  case E_V8SFmode:
    if (TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0))
{
 gen = gen_avx512vl_vpermt2varv8sf3;
 maskmode = V8SImode((void) 0, E_V8SImode);
}
    break;
  case E_V16SFmode:
    if (TARGET_AVX512F((global_options.x_ix86_isa_flags & (1UL << 15)) !=
 0))
{
 gen = gen_avx512f_vpermt2varv16sf3;
 maskmode = V16SImode((void) 0, E_V16SImode);
}
    break;
  case E_V2DImode:
    if (TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0))
gen = gen_avx512vl_vpermt2varv2di3;
    break;
  case E_V4DImode:
    if (TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0))
gen = gen_avx512vl_vpermt2varv4di3;
    break;
  case E_V8DImode:
    if (TARGET_AVX512F((global_options.x_ix86_isa_flags & (1UL << 15)) !=
 0))
gen = gen_avx512f_vpermt2varv8di3;
    break;
  case E_V2DFmode:
    if (TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0))
{
 gen = gen_avx512vl_vpermt2varv2df3;
 maskmode = V2DImode((void) 0, E_V2DImode);
}
    break;
  case E_V4DFmode:
    if (TARGET_AVX512VL((global_options.x_ix86_isa_flags & (1UL << 20)) !=
 0))
{
 gen = gen_avx512vl_vpermt2varv4df3;
 maskmode = V4DImode((void) 0, E_V4DImode);
}
    break;
  case E_V8DFmode:
    if (TARGET_AVX512F((global_options.x_ix86_isa_flags & (1UL << 15)) !=
 0))
{
 gen = gen_avx512f_vpermt2varv8df3;
 maskmode = V8DImode((void) 0, E_V8DImode);
}
    break;
  default:
    break;
  }

if (gen == NULL__null)
  return false;

/* ix86_expand_vec_perm_vpermt2 is called from both const and non-const
   expander, so args are either in d, or in op0, op1 etc.  */
if (d)
  {
    rtx vec[64];
    target = d->target;
    op0 = d->op0;
    op1 = d->op1;
    for (int i = 0; i < d->nelt; ++i)
vec[i] = GEN_INT (d->perm[i])gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (d->perm[i]));
    mask = gen_rtx_CONST_VECTOR (maskmode, gen_rtvec_v (d->nelt, vec));
  }

emit_insn (gen (target, force_reg (maskmode, mask), op0, op1));
return true;
4538}

4540/* Expand a variable vector permutation.  */

4542void
4543ix86_expand_vec_perm (rtx operands[])
4544{
rtx target = operands[0];
rtx op0 = operands[1];
rtx op1 = operands[2];
rtx mask = operands[3];
rtx t1, t2, t3, t4, t5, t6, t7, t8, vt, vt2, vec[32];
machine_mode mode = GET_MODE (op0)((machine_mode) (op0)->mode);
machine_mode maskmode = GET_MODE (mask)((machine_mode) (mask)->mode);
int w, e, i;
bool one_operand_shuffle = rtx_equal_p (op0, op1);

/* Number of elements in the vector.  */
w = GET_MODE_NUNITS (mode)(mode_to_nunits (mode).coeffs[0]);
e = GET_MODE_UNIT_SIZE (mode)mode_to_unit_size (mode);
gcc_assert (w <= 64)((void)(!(w <= 64) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 4558, __FUNCTION__), 0 : 0));

if (TARGET_AVX512F((global_options.x_ix86_isa_flags & (1UL << 15)) !=
 0) && one_operand_shuffle)
  {
    rtx (*gen) (rtx, rtx, rtx) = NULL__null;
    switch (mode)
{
case E_V16SImode:
 gen =gen_avx512f_permvarv16si;
 break;
case E_V16SFmode:
 gen = gen_avx512f_permvarv16sf;
 break;
case E_V8DImode:
 gen = gen_avx512f_permvarv8di;
 break;
case E_V8DFmode:
 gen = gen_avx512f_permvarv8df;
 break;
default:
 break;
}
    if (gen != NULL__null)
{
 emit_insn (gen (target, op0, mask));
 return;
}
  }

if (ix86_expand_vec_perm_vpermt2 (target, mask, op0, op1, NULL__null))
  return;

if (TARGET_AVX2((global_options.x_ix86_isa_flags & (1UL << 9)) != 0
))
  {
    if (mode == V4DImode((void) 0, E_V4DImode) || mode == V4DFmode((void) 0, E_V4DFmode) || mode == V16HImode((void) 0, E_V16HImode))
{
 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
    an constant shuffle operand.  With a tiny bit of effort we can
    use VPERMD instead.  A re-interpretation stall for V4DFmode is
    unfortunate but there's no avoiding it.
    Similarly for V16HImode we don't have instructions for variable
    shuffling, while for V32QImode we can use after preparing suitable
    masks vpshufb; vpshufb; vpermq; vpor.  */

 if (mode == V16HImode((void) 0, E_V16HImode))
   {
     maskmode = mode = V32QImode((void) 0, E_V32QImode);
     w = 32;
     e = 1;
   }
 else
   {
     maskmode = mode = V8SImode((void) 0, E_V8SImode);
     w = 8;
     e = 4;
   }
 t1 = gen_reg_rtx (maskmode);

 /* Replicate the low bits of the V4DImode mask into V8SImode:
      mask = { A B C D }
      t1 = { A A B B C C D D }.  */
 for (i = 0; i < w / 2; ++i)
   vec[i*2 + 1] = vec[i*2] = GEN_INT (i * 2)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (i * 2));
 vt = gen_rtx_CONST_VECTOR (maskmode, gen_rtvec_v (w, vec));
 vt = force_reg (maskmode, vt);
 mask = gen_lowpartrtl_hooks.gen_lowpart (maskmode, mask);
 if (maskmode == V8SImode((void) 0, E_V8SImode))
   emit_insn (gen_avx2_permvarv8si (t1, mask, vt));
 else
   emit_insn (gen_avx2_pshufbv32qi3 (t1, mask, vt));

 /* Multiply the shuffle indicies by two.  */
 t1 = expand_simple_binop (maskmode, PLUS, t1, t1, t1, 1,
		    OPTAB_DIRECT);

 /* Add one to the odd shuffle indicies:
t1 = { A*2, A*2+1, B*2, B*2+1, ... }.  */
 for (i = 0; i < w / 2; ++i)
   {
     vec[i * 2] = const0_rtx(const_int_rtx[64]);
     vec[i * 2 + 1] = const1_rtx(const_int_rtx[64 +1]);
   }
 vt = gen_rtx_CONST_VECTOR (maskmode, gen_rtvec_v (w, vec));
 vt = validize_mem (force_const_mem (maskmode, vt));
 t1 = expand_simple_binop (maskmode, PLUS, t1, vt, t1, 1,
		    OPTAB_DIRECT);

 /* Continue as if V8SImode (resp. V32QImode) was used initially.  */
 operands[3] = mask = t1;
 target = gen_reg_rtx (mode);
 op0 = gen_lowpartrtl_hooks.gen_lowpart (mode, op0);
 op1 = gen_lowpartrtl_hooks.gen_lowpart (mode, op1);
}

    switch (mode)
{
case E_V8SImode:
 /* The VPERMD and VPERMPS instructions already properly ignore
    the high bits of the shuffle elements.  No need for us to
    perform an AND ourselves.  */
 if (one_operand_shuffle)
   {
     emit_insn (gen_avx2_permvarv8si (target, op0, mask));
     if (target != operands[0])
emit_move_insn (operands[0],
		gen_lowpartrtl_hooks.gen_lowpart (GET_MODE (operands[0])((machine_mode) (operands[0])->mode), target));
   }
 else
   {
     t1 = gen_reg_rtx (V8SImode((void) 0, E_V8SImode));
     t2 = gen_reg_rtx (V8SImode((void) 0, E_V8SImode));
     emit_insn (gen_avx2_permvarv8si (t1, op0, mask));
     emit_insn (gen_avx2_permvarv8si (t2, op1, mask));
     goto merge_two;
   }
 return;

case E_V8SFmode:
 mask = gen_lowpartrtl_hooks.gen_lowpart (V8SImode((void) 0, E_V8SImode), mask);
 if (one_operand_shuffle)
   emit_insn (gen_avx2_permvarv8sf (target, op0, mask));
 else
   {
     t1 = gen_reg_rtx (V8SFmode((void) 0, E_V8SFmode));
     t2 = gen_reg_rtx (V8SFmode((void) 0, E_V8SFmode));
     emit_insn (gen_avx2_permvarv8sf (t1, op0, mask));
     emit_insn (gen_avx2_permvarv8sf (t2, op1, mask));
     goto merge_two;
   }
 return;

      case E_V4SImode:
 /* By combining the two 128-bit input vectors into one 256-bit
    input vector, we can use VPERMD and VPERMPS for the full
    two-operand shuffle.  */
 t1 = gen_reg_rtx (V8SImode((void) 0, E_V8SImode));
 t2 = gen_reg_rtx (V8SImode((void) 0, E_V8SImode));
 emit_insn (gen_avx_vec_concatv8si (t1, op0, op1));
 emit_insn (gen_avx_vec_concatv8si (t2, mask, mask));
 emit_insn (gen_avx2_permvarv8si (t1, t1, t2));
 emit_insn (gen_avx_vextractf128v8si (target, t1, const0_rtx(const_int_rtx[64])));
 return;

      case E_V4SFmode:
 t1 = gen_reg_rtx (V8SFmode((void) 0, E_V8SFmode));
 t2 = gen_reg_rtx (V8SImode((void) 0, E_V8SImode));
 mask = gen_lowpartrtl_hooks.gen_lowpart (V4SImode((void) 0, E_V4SImode), mask);
 emit_insn (gen_avx_vec_concatv8sf (t1, op0, op1));
 emit_insn (gen_avx_vec_concatv8si (t2, mask, mask));
 emit_insn (gen_avx2_permvarv8sf (t1, t1, t2));
 emit_insn (gen_avx_vextractf128v8sf (target, t1, const0_rtx(const_int_rtx[64])));
 return;

case E_V32QImode:
 t1 = gen_reg_rtx (V32QImode((void) 0, E_V32QImode));
 t2 = gen_reg_rtx (V32QImode((void) 0, E_V32QImode));
 t3 = gen_reg_rtx (V32QImode((void) 0, E_V32QImode));
 vt2 = GEN_INT (-128)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (-128));
 vt = gen_const_vec_duplicate (V32QImode((void) 0, E_V32QImode), vt2);
 vt = force_reg (V32QImode((void) 0, E_V32QImode), vt);
 for (i = 0; i < 32; i++)
   vec[i] = i < 16 ? vt2 : const0_rtx(const_int_rtx[64]);
 vt2 = gen_rtx_CONST_VECTOR (V32QImode((void) 0, E_V32QImode), gen_rtvec_v (32, vec));
 vt2 = force_reg (V32QImode((void) 0, E_V32QImode), vt2);
 /* From mask create two adjusted masks, which contain the same
    bits as mask in the low 7 bits of each vector element.
    The first mask will have the most significant bit clear
    if it requests element from the same 128-bit lane
    and MSB set if it requests element from the other 128-bit lane.
    The second mask will have the opposite values of the MSB,
    and additionally will have its 128-bit lanes swapped.
    E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
    t1   { 07 92 9e 09 ... | 17 19 85 1f ... } and
    t3   { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
    stands for other 12 bytes.  */
 /* The bit whether element is from the same lane or the other
    lane is bit 4, so shift it up by 3 to the MSB position.  */
 t5 = gen_reg_rtx (V4DImode((void) 0, E_V4DImode));
 emit_insn (gen_ashlv4di3 (t5, gen_lowpartrtl_hooks.gen_lowpart (V4DImode((void) 0, E_V4DImode), mask),
		    GEN_INT (3)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (3))));
 /* Clear MSB bits from the mask just in case it had them set.  */
 emit_insn (gen_avx2_andnotv32qi3 (t2, vt, mask));
 /* After this t1 will have MSB set for elements from other lane.  */
 emit_insn (gen_xorv32qi3 (t1, gen_lowpartrtl_hooks.gen_lowpart (V32QImode((void) 0, E_V32QImode), t5), vt2));
 /* Clear bits other than MSB.  */
 emit_insn (gen_andv32qi3 (t1, t1, vt));
 /* Or in the lower bits from mask into t3.  */
 emit_insn (gen_iorv32qi3 (t3, t1, t2));
 /* And invert MSB bits in t1, so MSB is set for elements from the same
    lane.  */
 emit_insn (gen_xorv32qi3 (t1, t1, vt));
 /* Swap 128-bit lanes in t3.  */
 t6 = gen_reg_rtx (V4DImode((void) 0, E_V4DImode));
 emit_insn (gen_avx2_permv4di_1 (t6, gen_lowpartrtl_hooks.gen_lowpart (V4DImode((void) 0, E_V4DImode), t3),
			  const2_rtx(const_int_rtx[64 +2]), GEN_INT (3)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (3)),
			  const0_rtx(const_int_rtx[64]), const1_rtx(const_int_rtx[64 +1])));
 /* And or in the lower bits from mask into t1.  */
 emit_insn (gen_iorv32qi3 (t1, t1, t2));
 if (one_operand_shuffle)
   {
     /* Each of these shuffles will put 0s in places where
 element from the other 128-bit lane is needed, otherwise
 will shuffle in the requested value.  */
     emit_insn (gen_avx2_pshufbv32qi3 (t3, op0,
				gen_lowpartrtl_hooks.gen_lowpart (V32QImode((void) 0, E_V32QImode), t6)));
     emit_insn (gen_avx2_pshufbv32qi3 (t1, op0, t1));
     /* For t3 the 128-bit lanes are swapped again.  */
     t7 = gen_reg_rtx (V4DImode((void) 0, E_V4DImode));
     emit_insn (gen_avx2_permv4di_1 (t7, gen_lowpartrtl_hooks.gen_lowpart (V4DImode((void) 0, E_V4DImode), t3),
			      const2_rtx(const_int_rtx[64 +2]), GEN_INT (3)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (3)),
			      const0_rtx(const_int_rtx[64]), const1_rtx(const_int_rtx[64 +1])));
     /* And oring both together leads to the result.  */
     emit_insn (gen_iorv32qi3 (target, t1,
			gen_lowpartrtl_hooks.gen_lowpart (V32QImode((void) 0, E_V32QImode), t7)));
     if (target != operands[0])
emit_move_insn (operands[0],
		gen_lowpartrtl_hooks.gen_lowpart (GET_MODE (operands[0])((machine_mode) (operands[0])->mode), target));
     return;
   }

 t4 = gen_reg_rtx (V32QImode((void) 0, E_V32QImode));
 /* Similarly to the above one_operand_shuffle code,
    just for repeated twice for each operand.  merge_two:
    code will merge the two results together.  */
 emit_insn (gen_avx2_pshufbv32qi3 (t4, op0,
			    gen_lowpartrtl_hooks.gen_lowpart (V32QImode((void) 0, E_V32QImode), t6)));
 emit_insn (gen_avx2_pshufbv32qi3 (t3, op1,
			    gen_lowpartrtl_hooks.gen_lowpart (V32QImode((void) 0, E_V32QImode), t6)));
 emit_insn (gen_avx2_pshufbv32qi3 (t2, op0, t1));
 emit_insn (gen_avx2_pshufbv32qi3 (t1, op1, t1));
 t7 = gen_reg_rtx (V4DImode((void) 0, E_V4DImode));
 emit_insn (gen_avx2_permv4di_1 (t7, gen_lowpartrtl_hooks.gen_lowpart (V4DImode((void) 0, E_V4DImode), t4),
			  const2_rtx(const_int_rtx[64 +2]), GEN_INT (3)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (3)),
			  const0_rtx(const_int_rtx[64]), const1_rtx(const_int_rtx[64 +1])));
 t8 = gen_reg_rtx (V4DImode((void) 0, E_V4DImode));
 emit_insn (gen_avx2_permv4di_1 (t8, gen_lowpartrtl_hooks.gen_lowpart (V4DImode((void) 0, E_V4DImode), t3),
			  const2_rtx(const_int_rtx[64 +2]), GEN_INT (3)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (3)),
			  const0_rtx(const_int_rtx[64]), const1_rtx(const_int_rtx[64 +1])));
 emit_insn (gen_iorv32qi3 (t4, t2, gen_lowpartrtl_hooks.gen_lowpart (V32QImode((void) 0, E_V32QImode), t7)));
 emit_insn (gen_iorv32qi3 (t3, t1, gen_lowpartrtl_hooks.gen_lowpart (V32QImode((void) 0, E_V32QImode), t8)));
 t1 = t4;
 t2 = t3;
 goto merge_two;

default:
 gcc_assert (GET_MODE_SIZE (mode) <= 16)((void)(!(((unsigned short) mode_to_bytes (mode).coeffs[0]) <=
 16) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 4803, __FUNCTION__), 0 : 0));
 break;
}
  }

if (TARGET_XOP((global_options.x_ix86_isa_flags & (1UL << 59)) !=
 0))
  {
    /* The XOP VPPERM insn supports three inputs.  By ignoring the 
one_operand_shuffle special case, we avoid creating another
set of constant vectors in memory.  */
    one_operand_shuffle = false;

    /* mask = mask & {2*w-1, ...} */
    vt = GEN_INT (2*w - 1)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (2*w - 1));
  }
else
  {
    /* mask = mask & {w-1, ...} */
    vt = GEN_INT (w - 1)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (w - 1));
  }

vt = gen_const_vec_duplicate (maskmode, vt);
mask = expand_simple_binop (maskmode, AND, mask, vt,
	      NULL_RTX(rtx) 0, 0, OPTAB_DIRECT);

/* For non-QImode operations, convert the word permutation control
   into a byte permutation control.  */
if (mode != V16QImode((void) 0, E_V16QImode))
  {
    mask = expand_simple_binop (maskmode, ASHIFT, mask,
		  GEN_INT (exact_log2 (e))gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (exact_log2 (e))),
		  NULL_RTX(rtx) 0, 0, OPTAB_DIRECT);

    /* Convert mask to vector of chars.  */
    mask = force_reg (V16QImode((void) 0, E_V16QImode), gen_lowpartrtl_hooks.gen_lowpart (V16QImode((void) 0, E_V16QImode), mask));

    /* Replicate each of the input bytes into byte positions:
(v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
(v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
(v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}.  */
    for (i = 0; i < 16; ++i)
vec[i] = GEN_INT (i/e * e)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (i/e * e));
    vt = gen_rtx_CONST_VECTOR (V16QImode((void) 0, E_V16QImode), gen_rtvec_v (16, vec));
    vt = validize_mem (force_const_mem (V16QImode((void) 0, E_V16QImode), vt));
    if (TARGET_XOP((global_options.x_ix86_isa_flags & (1UL << 59)) !=
 0))
emit_insn (gen_xop_pperm (mask, mask, mask, vt));
    else
emit_insn (gen_ssse3_pshufbv16qi3 (mask, mask, vt));

    /* Convert it into the byte positions by doing
mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...}  */
    for (i = 0; i < 16; ++i)
vec[i] = GEN_INT (i % e)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (i % e));
    vt = gen_rtx_CONST_VECTOR (V16QImode((void) 0, E_V16QImode), gen_rtvec_v (16, vec));
    vt = validize_mem (force_const_mem (V16QImode((void) 0, E_V16QImode), vt));
    emit_insn (gen_addv16qi3 (mask, mask, vt));
  }

/* The actual shuffle operations all operate on V16QImode.  */
op0 = gen_lowpartrtl_hooks.gen_lowpart (V16QImode((void) 0, E_V16QImode), op0);
op1 = gen_lowpartrtl_hooks.gen_lowpart (V16QImode((void) 0, E_V16QImode), op1);

if (TARGET_XOP((global_options.x_ix86_isa_flags & (1UL << 59)) !=
 0))
  {
    if (GET_MODE (target)((machine_mode) (target)->mode) != V16QImode((void) 0, E_V16QImode))
target = gen_reg_rtx (V16QImode((void) 0, E_V16QImode));
    emit_insn (gen_xop_pperm (target, op0, op1, mask));
    if (target != operands[0])
emit_move_insn (operands[0],
	gen_lowpartrtl_hooks.gen_lowpart (GET_MODE (operands[0])((machine_mode) (operands[0])->mode), target));
  }
else if (one_operand_shuffle)
  {
    if (GET_MODE (target)((machine_mode) (target)->mode) != V16QImode((void) 0, E_V16QImode))
target = gen_reg_rtx (V16QImode((void) 0, E_V16QImode));
    emit_insn (gen_ssse3_pshufbv16qi3 (target, op0, mask));
    if (target != operands[0])
emit_move_insn (operands[0],
	gen_lowpartrtl_hooks.gen_lowpart (GET_MODE (operands[0])((machine_mode) (operands[0])->mode), target));
  }
else
  {
    rtx xops[6];
    bool ok;

    /* Shuffle the two input vectors independently.  */
    t1 = gen_reg_rtx (V16QImode((void) 0, E_V16QImode));
    t2 = gen_reg_rtx (V16QImode((void) 0, E_V16QImode));
    emit_insn (gen_ssse3_pshufbv16qi3 (t1, op0, mask));
    emit_insn (gen_ssse3_pshufbv16qi3 (t2, op1, mask));

merge_two:
    /* Then merge them together.  The key is whether any given control
       element contained a bit set that indicates the second word.  */
    mask = operands[3];
    vt = GEN_INT (w)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (w));
    if (maskmode == V2DImode((void) 0, E_V2DImode) && !TARGET_SSE4_1((global_options.x_ix86_isa_flags & (1UL << 38)) !=
 0))
{
 /* Without SSE4.1, we don't have V2DImode EQ.  Perform one
    more shuffle to convert the V2DI input mask into a V4SI
    input mask.  At which point the masking that expand_int_vcond
    will work as desired.  */
 rtx t3 = gen_reg_rtx (V4SImode((void) 0, E_V4SImode));
 emit_insn (gen_sse2_pshufd_1 (t3, gen_lowpartrtl_hooks.gen_lowpart (V4SImode((void) 0, E_V4SImode), mask),
		        const0_rtx(const_int_rtx[64]), const0_rtx(const_int_rtx[64]),
		        const2_rtx(const_int_rtx[64 +2]), const2_rtx(const_int_rtx[64 +2])));
 mask = t3;
 maskmode = V4SImode((void) 0, E_V4SImode);
 e = w = 4;
}

    vt = gen_const_vec_duplicate (maskmode, vt);
    vt = force_reg (maskmode, vt);
    mask = expand_simple_binop (maskmode, AND, mask, vt,
		  NULL_RTX(rtx) 0, 0, OPTAB_DIRECT);

    if (GET_MODE (target)((machine_mode) (target)->mode) != mode)
target = gen_reg_rtx (mode);
    xops[0] = target;
    xops[1] = gen_lowpartrtl_hooks.gen_lowpart (mode, t2);
    xops[2] = gen_lowpartrtl_hooks.gen_lowpart (mode, t1);
    xops[3] = gen_rtx_EQ (maskmode, mask, vt)gen_rtx_fmt_ee_stat ((EQ), ((maskmode)), ((mask)), ((vt)) );
    xops[4] = mask;
    xops[5] = vt;
    ok = ix86_expand_int_vcond (xops);
    gcc_assert (ok)((void)(!(ok) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 4928, __FUNCTION__), 0 : 0));
    if (target != operands[0])
emit_move_insn (operands[0],
	gen_lowpartrtl_hooks.gen_lowpart (GET_MODE (operands[0])((machine_mode) (operands[0])->mode), target));
  }
4933}

4935/* Unpack OP[1] into the next wider integer vector type.  UNSIGNED_P is
 true if we should do zero extension, else sign extension.  HIGH_P is
 true if we want the N/2 high elements, else the low elements.  */

4939void
4940ix86_expand_sse_unpack (rtx dest, rtx src, bool unsigned_p, bool high_p)
4941{
machine_mode imode = GET_MODE (src)((machine_mode) (src)->mode);
rtx tmp;

if (TARGET_SSE4_1((global_options.x_ix86_isa_flags & (1UL << 38)) !=
 0))
3
←
Assuming the condition is true→
4
←
Taking true branch→
  {
    rtx (*unpack)(rtx, rtx);
    rtx (*extract)(rtx, rtx) = NULL__null;
5
←
'extract' initialized to a null pointer value→
    machine_mode halfmode = BLKmode((void) 0, E_BLKmode);

    switch (imode)
6
←
Control jumps to 'case E_V16QImode:'  at line 5007→
{
case E_V64QImode:
 if (unsigned_p)
   unpack = gen_avx512bw_zero_extendv32qiv32hi2;
 else
   unpack = gen_avx512bw_sign_extendv32qiv32hi2;
 halfmode = V32QImode((void) 0, E_V32QImode);
 extract
   = high_p ? gen_vec_extract_hi_v64qi : gen_vec_extract_lo_v64qi;
 break;
case E_V32QImode:
 if (unsigned_p)
   unpack = gen_avx2_zero_extendv16qiv16hi2;
 else
   unpack = gen_avx2_sign_extendv16qiv16hi2;
 halfmode = V16QImode((void) 0, E_V16QImode);
 extract
   = high_p ? gen_vec_extract_hi_v32qi : gen_vec_extract_lo_v32qi;
 break;
case E_V32HImode:
 if (unsigned_p)
   unpack = gen_avx512f_zero_extendv16hiv16si2;
 else
   unpack = gen_avx512f_sign_extendv16hiv16si2;
 halfmode = V16HImode((void) 0, E_V16HImode);
 extract
   = high_p ? gen_vec_extract_hi_v32hi : gen_vec_extract_lo_v32hi;
 break;
case E_V16HImode:
 if (unsigned_p)
   unpack = gen_avx2_zero_extendv8hiv8si2;
 else
   unpack = gen_avx2_sign_extendv8hiv8si2;
 halfmode = V8HImode((void) 0, E_V8HImode);
 extract
   = high_p ? gen_vec_extract_hi_v16hi : gen_vec_extract_lo_v16hi;
 break;
case E_V16SImode:
 if (unsigned_p)
   unpack = gen_avx512f_zero_extendv8siv8di2;
 else
   unpack = gen_avx512f_sign_extendv8siv8di2;
 halfmode = V8SImode((void) 0, E_V8SImode);
 extract
   = high_p ? gen_vec_extract_hi_v16si : gen_vec_extract_lo_v16si;
 break;
case E_V8SImode:
 if (unsigned_p)
   unpack = gen_avx2_zero_extendv4siv4di2;
 else
   unpack = gen_avx2_sign_extendv4siv4di2;
 halfmode = V4SImode((void) 0, E_V4SImode);
 extract
   = high_p ? gen_vec_extract_hi_v8si : gen_vec_extract_lo_v8si;
 break;
case E_V16QImode:
 if (unsigned_p)
7
←
Assuming 'unsigned_p' is false→
8
←
Taking false branch→
   unpack = gen_sse4_1_zero_extendv8qiv8hi2;
 else
   unpack = gen_sse4_1_sign_extendv8qiv8hi2;
 break;
9
←
 Execution continues on line 5029→
case E_V8HImode:
 if (unsigned_p)
   unpack = gen_sse4_1_zero_extendv4hiv4si2;
 else
   unpack = gen_sse4_1_sign_extendv4hiv4si2;
 break;
case E_V4SImode:
 if (unsigned_p)
   unpack = gen_sse4_1_zero_extendv2siv2di2;
 else
   unpack = gen_sse4_1_sign_extendv2siv2di2;
 break;
default:
 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5026, __FUNCTION__));
}

    if (GET_MODE_SIZE (imode)((unsigned short) mode_to_bytes (imode).coeffs[0]) >= 32)
10
←
Assuming the condition is true→
11
←
Taking true branch→
{
 tmp = gen_reg_rtx (halfmode);
 emit_insn (extract (tmp, src));
12
←
Called function pointer is null (null dereference)
}
    else if (high_p)
{
 /* Shift higher 8 bytes to lower 8 bytes.  */
 tmp = gen_reg_rtx (V1TImode((void) 0, E_V1TImode));
 emit_insn (gen_sse2_lshrv1ti3 (tmp, gen_lowpartrtl_hooks.gen_lowpart (V1TImode((void) 0, E_V1TImode), src),
			 GEN_INT (64)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (64))));
 tmp = gen_lowpartrtl_hooks.gen_lowpart (imode, tmp);
}
    else
tmp = src;

    emit_insn (unpack (dest, tmp));
  }
else
  {
    rtx (*unpack)(rtx, rtx, rtx);

    switch (imode)
{
case E_V16QImode:
 if (high_p)
   unpack = gen_vec_interleave_highv16qi;
 else
   unpack = gen_vec_interleave_lowv16qi;
 break;
case E_V8HImode:
 if (high_p)
   unpack = gen_vec_interleave_highv8hi;
 else
   unpack = gen_vec_interleave_lowv8hi;
 break;
case E_V4SImode:
 if (high_p)
   unpack = gen_vec_interleave_highv4si;
 else
   unpack = gen_vec_interleave_lowv4si;
 break;
default:
 gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5072, __FUNCTION__));
}

    if (unsigned_p)
tmp = force_reg (imode, CONST0_RTX (imode)(const_tiny_rtx[0][(int) (imode)]));
    else
tmp = ix86_expand_sse_cmp (gen_reg_rtx (imode), GT, CONST0_RTX (imode)(const_tiny_rtx[0][(int) (imode)]),
		   src, pc_rtx, pc_rtx);

    rtx tmp2 = gen_reg_rtx (imode);
    emit_insn (unpack (tmp2, src, tmp));
    emit_move_insn (dest, gen_lowpartrtl_hooks.gen_lowpart (GET_MODE (dest)((machine_mode) (dest)->mode), tmp2));
  }
5085}

5087/* Split operands 0 and 1 into half-mode parts.  Similar to split_double_mode,
 but works for floating pointer parameters and nonoffsetable memories.
 For pushes, it returns just stack offsets; the values will be saved
 in the right order.  Maximally three parts are generated.  */

5092static int
5093ix86_split_to_parts (rtx operand, rtx *parts, machine_mode mode)
5094{
int size;

if (!TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
))
  size = mode==XFmode(scalar_float_mode ((scalar_float_mode::from_int) E_XFmode)) ? 3 : GET_MODE_SIZE (mode)((unsigned short) mode_to_bytes (mode).coeffs[0]) / 4;
else
  size = (GET_MODE_SIZE (mode)((unsigned short) mode_to_bytes (mode).coeffs[0]) + 4) / 8;

gcc_assert (!REG_P (operand) || !MMX_REGNO_P (REGNO (operand)))((void)(!(!(((enum rtx_code) (operand)->code) == REG) || !
((unsigned long) (((rhs_regno(operand)))) - (unsigned long) (
28) <= (unsigned long) (35) - (unsigned long) (28))) ? fancy_abort
 ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5102, __FUNCTION__), 0 : 0));
gcc_assert (size >= 2 && size <= 4)((void)(!(size >= 2 && size <= 4) ? fancy_abort
 ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5103, __FUNCTION__), 0 : 0));

/* Optimize constant pool reference to immediates.  This is used by fp
   moves, that force all constants to memory to allow combining.  */
if (MEM_P (operand)(((enum rtx_code) (operand)->code) == MEM) && MEM_READONLY_P (operand)(__extension__ ({ __typeof ((operand)) const _rtx = ((operand
)); if (((enum rtx_code) (_rtx)->code) != MEM) rtl_check_failed_flag
 ("MEM_READONLY_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5107, __FUNCTION__); _rtx; })->unchanging))
  operand = avoid_constant_pool_reference (operand);

if (MEM_P (operand)(((enum rtx_code) (operand)->code) == MEM) && !offsettable_memref_p (operand))
  {
    /* The only non-offsetable memories we handle are pushes.  */
    int ok = push_operand (operand, VOIDmode((void) 0, E_VOIDmode));

    gcc_assert (ok)((void)(!(ok) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5115, __FUNCTION__), 0 : 0));

    operand = copy_rtx (operand);
    PUT_MODE (operand, word_mode);
    parts[0] = parts[1] = parts[2] = parts[3] = operand;
    return size;
  }

if (GET_CODE (operand)((enum rtx_code) (operand)->code) == CONST_VECTOR)
  {
    scalar_int_mode imode = int_mode_for_mode (mode).require ();
    /* Caution: if we looked through a constant pool memory above,
the operand may actually have a different mode now.  That's
ok, since we want to pun this all the way back to an integer.  */
    operand = simplify_subreg (imode, operand, GET_MODE (operand)((machine_mode) (operand)->mode), 0);
    gcc_assert (operand != NULL)((void)(!(operand != __null) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5130, __FUNCTION__), 0 : 0));
    mode = imode;
  }

if (!TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
))
  {
    if (mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)))
split_double_mode (mode, &operand, 1, &parts[0], &parts[1]);
    else
{
 int i;

 if (REG_P (operand)(((enum rtx_code) (operand)->code) == REG))
   {
     gcc_assert (reload_completed)((void)(!(reload_completed) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5144, __FUNCTION__), 0 : 0));
     for (i = 0; i < size; i++)
parts[i] = gen_rtx_REG (SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)), REGNO (operand)(rhs_regno(operand)) + i);
   }
 else if (offsettable_memref_p (operand))
   {
     operand = adjust_address (operand, SImode, 0)adjust_address_1 (operand, (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)), 0, 1, 1, 0, 0);
     parts[0] = operand;
     for (i = 1; i < size; i++)
parts[i] = adjust_address (operand, SImode, 4 * i)adjust_address_1 (operand, (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode)), 4 * i, 1, 1, 0, 0);
   }
 else if (CONST_DOUBLE_P (operand)(((enum rtx_code) (operand)->code) == CONST_DOUBLE))
   {
     const REAL_VALUE_TYPEstruct real_value *r;
     long l[4];

     r = CONST_DOUBLE_REAL_VALUE (operand)((const struct real_value *) (&(operand)->u.rv));
     switch (mode)
{
case E_TFmode:
  real_to_target (l, r, mode);
  parts[3] = gen_int_mode (l[3], SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)));
  parts[2] = gen_int_mode (l[2], SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)));
  break;
case E_XFmode:
  /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
     long double may not be 80-bit.  */
  real_to_target (l, r, mode);
  parts[2] = gen_int_mode (l[2], SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)));
  break;
case E_DFmode:
  REAL_VALUE_TO_TARGET_DOUBLE (*r, l)real_to_target (l, &(*r), float_mode_for_size (64).require
 ());
  break;
default:
  gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5178, __FUNCTION__));
}
     parts[1] = gen_int_mode (l[1], SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)));
     parts[0] = gen_int_mode (l[0], SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)));
   }
 else
   gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5184, __FUNCTION__));
}
  }
else
  {
    if (mode == TImode(scalar_int_mode ((scalar_int_mode::from_int) E_TImode)))
split_double_mode (mode, &operand, 1, &parts[0], &parts[1]);
    if (mode == XFmode(scalar_float_mode ((scalar_float_mode::from_int) E_XFmode)) || mode == TFmode(scalar_float_mode ((scalar_float_mode::from_int) E_TFmode)))
{
 machine_mode upper_mode = mode==XFmode(scalar_float_mode ((scalar_float_mode::from_int) E_XFmode)) ? SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)) : DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode));
 if (REG_P (operand)(((enum rtx_code) (operand)->code) == REG))
   {
     gcc_assert (reload_completed)((void)(!(reload_completed) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5196, __FUNCTION__), 0 : 0));
     parts[0] = gen_rtx_REG (DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)), REGNO (operand)(rhs_regno(operand)) + 0);
     parts[1] = gen_rtx_REG (upper_mode, REGNO (operand)(rhs_regno(operand)) + 1);
   }
 else if (offsettable_memref_p (operand))
   {
     operand = adjust_address (operand, DImode, 0)adjust_address_1 (operand, (scalar_int_mode ((scalar_int_mode
::from_int) E_DImode)), 0, 1, 1, 0, 0);
     parts[0] = operand;
     parts[1] = adjust_address (operand, upper_mode, 8)adjust_address_1 (operand, upper_mode, 8, 1, 1, 0, 0);
   }
 else if (CONST_DOUBLE_P (operand)(((enum rtx_code) (operand)->code) == CONST_DOUBLE))
   {
     long l[4];

     real_to_target (l, CONST_DOUBLE_REAL_VALUE (operand)((const struct real_value *) (&(operand)->u.rv)), mode);

     /* real_to_target puts 32-bit pieces in each long.  */
     parts[0] = gen_int_mode ((l[0] & HOST_WIDE_INT_C (0xffffffff)0xffffffffL)
		       | ((l[1] & HOST_WIDE_INT_C (0xffffffff)0xffffffffL)
			  << 32), DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)));

     if (upper_mode == SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)))
       parts[1] = gen_int_mode (l[2], SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)));
     else
       parts[1]
  = gen_int_mode ((l[2] & HOST_WIDE_INT_C (0xffffffff)0xffffffffL)
		  | ((l[3] & HOST_WIDE_INT_C (0xffffffff)0xffffffffL)
		     << 32), DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)));
   }
 else
   gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5226, __FUNCTION__));
}
  }

return size;
5231}

5233/* Emit insns to perform a move or push of DI, DF, XF, and TF values.
 Return false when normal moves are needed; true when all required
 insns have been emitted.  Operands 2-4 contain the input values
 int the correct order; operands 5-7 contain the output values.  */

5238void
5239ix86_split_long_move (rtx operands[])
5240{
rtx part[2][4];
int nparts, i, j;
int push = 0;
int collisions = 0;
machine_mode mode = GET_MODE (operands[0])((machine_mode) (operands[0])->mode);
bool collisionparts[4];

/* The DFmode expanders may ask us to move double.
   For 64bit target this is single move.  By hiding the fact
   here we simplify i386.md splitters.  */
if (TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
) && GET_MODE_SIZE (GET_MODE (operands[0]))((unsigned short) mode_to_bytes (((machine_mode) (operands[0]
)->mode)).coeffs[0]) == 8)
  {
    /* Optimize constant pool reference to immediates.  This is used by
fp moves, that force all constants to memory to allow combining.  */

    if (MEM_P (operands[1])(((enum rtx_code) (operands[1])->code) == MEM)
 && GET_CODE (XEXP (operands[1], 0))((enum rtx_code) ((((operands[1])->u.fld[0]).rt_rtx))->
code) == SYMBOL_REF
 && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))(__extension__ ({ __typeof (((((operands[1])->u.fld[0]).rt_rtx
))) const _rtx = (((((operands[1])->u.fld[0]).rt_rtx))); if
 (((enum rtx_code) (_rtx)->code) != SYMBOL_REF) rtl_check_failed_flag
 ("CONSTANT_POOL_ADDRESS_P", _rtx, "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5258, __FUNCTION__); _rtx; })->unchanging))
operands[1] = get_pool_constant (XEXP (operands[1], 0)(((operands[1])->u.fld[0]).rt_rtx));
    if (push_operand (operands[0], VOIDmode((void) 0, E_VOIDmode)))
{
 operands[0] = copy_rtx (operands[0]);
 PUT_MODE (operands[0], word_mode);
}
    else
      operands[0] = gen_lowpartrtl_hooks.gen_lowpart (DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)), operands[0]);
    operands[1] = gen_lowpartrtl_hooks.gen_lowpart (DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)), operands[1]);
    emit_move_insn (operands[0], operands[1]);
    return;
  }

/* The only non-offsettable memory we handle is push.  */
if (push_operand (operands[0], VOIDmode((void) 0, E_VOIDmode)))
  push = 1;
else
  gcc_assert (!MEM_P (operands[0])((void)(!(!(((enum rtx_code) (operands[0])->code) == MEM) ||
 offsettable_memref_p (operands[0])) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5277, __FUNCTION__), 0 : 0))
|| offsettable_memref_p (operands[0]))((void)(!(!(((enum rtx_code) (operands[0])->code) == MEM) ||
 offsettable_memref_p (operands[0])) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5277, __FUNCTION__), 0 : 0));

nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0])((machine_mode) (operands[0])->mode));
ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0])((machine_mode) (operands[0])->mode));

/* When emitting push, take care for source operands on the stack.  */
if (push && MEM_P (operands[1])(((enum rtx_code) (operands[1])->code) == MEM)
    && reg_overlap_mentioned_p (stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]), operands[1]))
  {
    rtx src_base = XEXP (part[1][nparts - 1], 0)(((part[1][nparts - 1])->u.fld[0]).rt_rtx);

    /* Compensate for the stack decrement by 4.  */
    if (!TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
) && nparts == 3
 && mode == XFmode(scalar_float_mode ((scalar_float_mode::from_int) E_XFmode)) && TARGET_128BIT_LONG_DOUBLE((global_options.x_target_flags & (1U << 0)) != 0))
src_base = plus_constant (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), src_base, 4);

    /* src_base refers to the stack pointer and is
automatically decreased by emitted push.  */
    for (i = 0; i < nparts; i++)
part[1][i] = change_address (part[1][i],
		     GET_MODE (part[1][i])((machine_mode) (part[1][i])->mode), src_base);
  }

/* We need to do copy in the right order in case an address register
   of the source overlaps the destination.  */
if (REG_P (part[0][0])(((enum rtx_code) (part[0][0])->code) == REG) && MEM_P (part[1][0])(((enum rtx_code) (part[1][0])->code) == MEM))
  {
    rtx tmp;

    for (i = 0; i < nparts; i++)
{
 collisionparts[i]
   = reg_overlap_mentioned_p (part[0][i], XEXP (part[1][0], 0)(((part[1][0])->u.fld[0]).rt_rtx));
 if (collisionparts[i])
   collisions++;
}

    /* Collision in the middle part can be handled by reordering.  */
    if (collisions == 1 && nparts == 3 && collisionparts [1])
{
 std::swap (part[0][1], part[0][2]);
 std::swap (part[1][1], part[1][2]);
}
    else if (collisions == 1
      && nparts == 4
      && (collisionparts [1] || collisionparts [2]))
{
 if (collisionparts [1])
   {
     std::swap (part[0][1], part[0][2]);
     std::swap (part[1][1], part[1][2]);
   }
 else
   {
     std::swap (part[0][2], part[0][3]);
     std::swap (part[1][2], part[1][3]);
   }
}

    /* If there are more collisions, we can't handle it by reordering.
Do an lea to the last part and use only one colliding move.  */
    else if (collisions > 1)
{
 rtx base, addr;

 collisions = 1;

 base = part[0][nparts - 1];

 /* Handle the case when the last part isn't valid for lea.
    Happens in 64-bit mode storing the 12-byte XFmode.  */
 if (GET_MODE (base)((machine_mode) (base)->mode) != Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))))
   base = gen_rtx_REG (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), REGNO (base)(rhs_regno(base)));

 addr = XEXP (part[1][0], 0)(((part[1][0])->u.fld[0]).rt_rtx);
 if (TARGET_TLS_DIRECT_SEG_REFS((global_options.x_target_flags & (1U << 27)) != 0))
   {
     struct ix86_address parts;
     int ok = ix86_decompose_address (addr, &parts);
     gcc_assert (ok)((void)(!(ok) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5356, __FUNCTION__), 0 : 0));
     /* It is not valid to use %gs: or %fs: in lea.  */
     gcc_assert (parts.seg == ADDR_SPACE_GENERIC)((void)(!(parts.seg == 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5358, __FUNCTION__), 0 : 0));
   }
 emit_insn (gen_rtx_SET (base, addr)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((base)
), ((addr)) ));
 part[1][0] = replace_equiv_address (part[1][0], base);
 for (i = 1; i < nparts; i++)
   {
     tmp = plus_constant (Pmode(global_options.x_ix86_pmode == PMODE_DI ? (scalar_int_mode (
(scalar_int_mode::from_int) E_DImode)) : (scalar_int_mode ((scalar_int_mode
::from_int) E_SImode))), base, UNITS_PER_WORD(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
 0) ? 8 : 4) * i);
     part[1][i] = replace_equiv_address (part[1][i], tmp);
   }
}
  }

if (push)
  {
    if (!TARGET_64BIT((global_options.x_ix86_isa_flags & (1UL << 1)) != 0
))
{
 if (nparts == 3)
   {
     if (TARGET_128BIT_LONG_DOUBLE((global_options.x_target_flags & (1U << 0)) != 0) && mode == XFmode(scalar_float_mode ((scalar_float_mode::from_int) E_XFmode)))
              emit_insn (gen_add2_insn (stack_pointer_rtx((this_target_rtl->x_global_rtl)[GR_STACK_POINTER]), GEN_INT (-4)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (-4))));
     emit_move_insn (part[0][2], part[1][2]);
   }
 else if (nparts == 4)
   {
     emit_move_insn (part[0][3], part[1][3]);
     emit_move_insn (part[0][2], part[1][2]);
   }
}
    else
{
 /* In 64bit mode we don't have 32bit push available.  In case this is
    register, it is OK - we will just use larger counterpart.  We also
    retype memory - these comes from attempt to avoid REX prefix on
    moving of second half of TFmode value.  */
 if (GET_MODE (part[1][1])((machine_mode) (part[1][1])->mode) == SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)))
   {
     switch (GET_CODE (part[1][1])((enum rtx_code) (part[1][1])->code))
{
case MEM:
  part[1][1] = adjust_address (part[1][1], DImode, 0)adjust_address_1 (part[1][1], (scalar_int_mode ((scalar_int_mode
::from_int) E_DImode)), 0, 1, 1, 0, 0);
  break;

case REG:
  part[1][1] = gen_rtx_REG (DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)), REGNO (part[1][1])(rhs_regno(part[1][1])));
  break;

default:
  gcc_unreachable ()(fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/config/i386/i386-expand.c"
, 5405, __FUNCTION__));
}

     if (GET_MODE (part[1][0])((machine_mode) (part[1][0])->mode) == SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)))
part[1][0] = part[1][1];
   }
}
    emit_move_insn (part[0][1], part[1][1]);
    emit_move_insn (part[0][0], part[1][0]);
    return;
  }

/* Choose correct order to not overwrite the source before it is copied.  */
if ((REG_P (part[0][0])(((enum rtx_code) (part[0][0])->code) == REG)
     && REG_P (part[1][1])(((enum rtx_code) (part[1][1])->code) == REG)
     && (REGNO (part[0][0])(rhs_regno(part[0][0])) == REGNO (part[1][1])(rhs_regno(part[1][1]))
  || (nparts == 3
      && REGNO (part[0][0])(rhs_regno(part[0][0])) == REGNO (part[1][2])(rhs_regno(part[1][2])))
  || (nparts == 4
      && REGNO (part[0][0])(rhs_regno(part[0][0])) == REGNO (part[1][3])(rhs_regno(part[1][3])))))
    || (collisions > 0
 && reg_overlap_mentioned_p (part[0][0], XEXP (part[1][0], 0)(((part[1][0])->u.fld[0]).rt_rtx))))
  {
    for (i = 0, j = nparts - 1; i < nparts; i++, j--)
{
 operands[2 + i] = part[0][j];
 operands[6 + i] = part[1][j];
}
  }
else
  {
    for (i = 0; i < nparts; i++)
{
 operands[2 + i] = part[0][i];
 operands[6 + i] = part[1][i];
}
  }

/* If optimizing for size, attempt to locally unCSE nonzero constants.  */
if (optimize_insn_for_size_p ())
  {
    for (j = 0; j < nparts - 1; j++)
if (CONST_INT_P (operands[6 + j])(((enum rtx_code) (operands[6 + j])->code) == CONST_INT)
   && operands[6 + j] != const0_rtx(const_int_rtx[64])
   && REG_P (operands[2 + j])(((enum rtx_code) (operands[2 + j])->code) == REG))
 for (i = j; i < nparts - 1; i++)
   if (CONST_INT_P (operands[7 + i])(((enum rtx_code) (operands[7 + i])->code) == CONST_INT)
&& INTVAL (operands[7 + i])((operands[7 + i])->u.hwint[0]) == INTVAL (operands[6 + j])((operands[6 + j])->u.hwint[0]))
     operands[7 + i] = operands[2 + j];
  }

for (i = 0; i < nparts; i++)
  emit_move_insn (operands[2 + i], operands[6 + i]);

return;
5460}

5462/* Helper function of ix86_split_ashl used to generate an SImode/DImode
 left shift by a constant, either using a single shift or
 a sequence of add instructions.  */

5466static void
5467ix86_expand_ashl_const (rtx operand, int count, machine_mode mode)
5468{
if (count == 1
    || (count * ix86_cost->add <= ix86_cost->shift_const
 && !optimize_insn_for_size_p ()))
  {
    while (count-- > 0)
emit_insn (gen_add2_insn (operand, operand));
  }
else
  {
    rtx (*insn)(rtx, rtx, rtx);

    insn = mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) ? gen_ashlsi3 : gen_ashldi3;
    emit_insn (insn (operand, operand, GEN_INT (count)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (count))));
  }
5483}

5485void
5486ix86_split_ashl (rtx *operands, rtx scratch, machine_mode mode)
5487{
rtx (*gen_ashl3)(rtx, rtx, rtx);
rtx (*gen_shld)(rtx, rtx, rtx);
int half_width = GET_MODE_BITSIZE (mode)((unsigned short) mode_to_bits (mode).coeffs[0]) >> 1;
machine_mode half_mode;

rtx low[2], high[2];
int count;

if (CONST_INT_P (operands[2])(((enum rtx_code) (operands[2])->code) == CONST_INT))
  {
    split_double_mode (mode, operands, 2, low, high);
    count = INTVAL (operands[2])((operands[2])->u.hwint[0]) & (GET_MODE_BITSIZE (mode)((unsigned short) mode_to_bits (mode).coeffs[0]) - 1);

    if (count >= half_width)
{
 emit_move_insn (high[0], low[1]);
 emit_move_insn (low[0], const0_rtx(const_int_rtx[64]));

 if (count > half_width)
   ix86_expand_ashl_const (high[0], count - half_width, mode);
}
    else
{
 gen_shld = mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) ? gen_x86_shld : gen_x86_64_shld;

 if (!rtx_equal_p (operands[0], operands[1]))
   emit_move_insn (operands[0], operands[1]);

 emit_insn (gen_shld (high[0], low[0], GEN_INT (count)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (count))));
 ix86_expand_ashl_const (low[0], count, mode);
}
    return;
  }

split_double_mode (mode, operands, 1, low, high);
half_mode = mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) ? SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)) : DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode));

gen_ashl3 = mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) ? gen_ashlsi3 : gen_ashldi3;

if (operands[1] == const1_rtx(const_int_rtx[64 +1]))
  {
    /* Assuming we've chosen a QImode capable registers, then 1 << N
can be done with two 32/64-bit shifts, no branches, no cmoves.  */
    if (ANY_QI_REG_P (low[0])((((enum rtx_code) (low[0])->code) == REG) && (((global_options
.x_ix86_isa_flags & (1UL << 1)) != 0) ? ((((unsigned
 long) (((rhs_regno(low[0])))) - (unsigned long) (0) <= (unsigned
 long) (7) - (unsigned long) (0))) || ((unsigned long) (((rhs_regno
(low[0])))) - (unsigned long) (36) <= (unsigned long) (43)
 - (unsigned long) (36))) : ((unsigned long) (((rhs_regno(low
[0])))) - (unsigned long) (0) <= (unsigned long) (3) - (unsigned
 long) (0)))) && ANY_QI_REG_P (high[0])((((enum rtx_code) (high[0])->code) == REG) && (((
global_options.x_ix86_isa_flags & (1UL << 1)) != 0)
 ? ((((unsigned long) (((rhs_regno(high[0])))) - (unsigned long
) (0) <= (unsigned long) (7) - (unsigned long) (0))) || ((
unsigned long) (((rhs_regno(high[0])))) - (unsigned long) (36
) <= (unsigned long) (43) - (unsigned long) (36))) : ((unsigned
 long) (((rhs_regno(high[0])))) - (unsigned long) (0) <= (
unsigned long) (3) - (unsigned long) (0)))))
{
 rtx s, d, flags = gen_rtx_REG (CCZmode((void) 0, E_CCZmode), FLAGS_REG17);

 ix86_expand_clear (low[0]);
 ix86_expand_clear (high[0]);
 emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (half_width)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (half_width))));

 d = gen_lowpartrtl_hooks.gen_lowpart (QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)), low[0]);
 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d)gen_rtx_fmt_e_stat ((STRICT_LOW_PART), ((((void) 0, E_VOIDmode
))), ((d)) );
 s = gen_rtx_EQ (QImode, flags, const0_rtx)gen_rtx_fmt_ee_stat ((EQ), (((scalar_int_mode ((scalar_int_mode
::from_int) E_QImode)))), ((flags)), (((const_int_rtx[64]))) );
 emit_insn (gen_rtx_SET (d, s)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((d)), (
(s)) ));

 d = gen_lowpartrtl_hooks.gen_lowpart (QImode(scalar_int_mode ((scalar_int_mode::from_int) E_QImode)), high[0]);
 d = gen_rtx_STRICT_LOW_PART (VOIDmode, d)gen_rtx_fmt_e_stat ((STRICT_LOW_PART), ((((void) 0, E_VOIDmode
))), ((d)) );
 s = gen_rtx_NE (QImode, flags, const0_rtx)gen_rtx_fmt_ee_stat ((NE), (((scalar_int_mode ((scalar_int_mode
::from_int) E_QImode)))), ((flags)), (((const_int_rtx[64]))) );
 emit_insn (gen_rtx_SET (d, s)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((d)), (
(s)) ));
}

    /* Otherwise, we can get the same results by manually performing
a bit extract operation on bit 5/6, and then performing the two
shifts.  The two methods of getting 0/1 into low/high are exactly
the same size.  Avoiding the shift in the bit extract case helps
pentium4 a bit; no one else seems to care much either way.  */
    else
{
 rtx (*gen_lshr3)(rtx, rtx, rtx);
 rtx (*gen_and3)(rtx, rtx, rtx);
 rtx (*gen_xor3)(rtx, rtx, rtx);
 HOST_WIDE_INTlong bits;
 rtx x;

 if (mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)))
   {
     gen_lshr3 = gen_lshrsi3;
     gen_and3 = gen_andsi3;
     gen_xor3 = gen_xorsi3;
     bits = 5;
   }
 else
   {
     gen_lshr3 = gen_lshrdi3;
     gen_and3 = gen_anddi3;
     gen_xor3 = gen_xordi3;
     bits = 6;
   }

 if (TARGET_PARTIAL_REG_STALLix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] && !optimize_insn_for_size_p ())
   x = gen_rtx_ZERO_EXTEND (half_mode, operands[2])gen_rtx_fmt_e_stat ((ZERO_EXTEND), ((half_mode)), ((operands[
2])) );
 else
   x = gen_lowpartrtl_hooks.gen_lowpart (half_mode, operands[2]);
 emit_insn (gen_rtx_SET (high[0], x)gen_rtx_fmt_ee_stat ((SET), (((void) 0, E_VOIDmode)), ((high[
0])), ((x)) ));

 emit_insn (gen_lshr3 (high[0], high[0], GEN_INT (bits)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (bits))));
 emit_insn (gen_and3 (high[0], high[0], const1_rtx(const_int_rtx[64 +1])));
 emit_move_insn (low[0], high[0]);
 emit_insn (gen_xor3 (low[0], low[0], const1_rtx(const_int_rtx[64 +1])));
}

    emit_insn (gen_ashl3 (low[0], low[0], operands[2]));
    emit_insn (gen_ashl3 (high[0], high[0], operands[2]));
    return;
  }

if (operands[1] == constm1_rtx(const_int_rtx[64 -1]))
  {
    /* For -1 << N, we can avoid the shld instruction, because we
know that we're shifting 0...31/63 ones into a -1.  */
    emit_move_insn (low[0], constm1_rtx(const_int_rtx[64 -1]));
    if (optimize_insn_for_size_p ())
emit_move_insn (high[0], low[0]);
    else
emit_move_insn (high[0], constm1_rtx(const_int_rtx[64 -1]));
  }
else
  {
    gen_shld = mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) ? gen_x86_shld : gen_x86_64_shld;

    if (!rtx_equal_p (operands[0], operands[1]))
emit_move_insn (operands[0], operands[1]);

    split_double_mode (mode, operands, 1, low, high);
    emit_insn (gen_shld (high[0], low[0], operands[2]));
  }

emit_insn (gen_ashl3 (low[0], low[0], operands[2]));

if (TARGET_CMOVE(ix86_arch_features[X86_ARCH_CMOV] || ((global_options.x_ix86_isa_flags
 & (1UL << 50)) != 0) || ((global_options.x_ix86_isa_flags
 & (1UL << 44)) != 0)) && scratch)
  {
    ix86_expand_clear (scratch);
    emit_insn (gen_x86_shift_adj_1
 (half_mode, high[0], low[0], operands[2], scratch));
  }
else
  emit_insn (gen_x86_shift_adj_2 (half_mode, high[0], low[0], operands[2]));
5626}

5628void
5629ix86_split_ashr (rtx *operands, rtx scratch, machine_mode mode)
5630{
rtx (*gen_ashr3)(rtx, rtx, rtx)
  = mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) ? gen_ashrsi3 : gen_ashrdi3;
rtx (*gen_shrd)(rtx, rtx, rtx);
int half_width = GET_MODE_BITSIZE (mode)((unsigned short) mode_to_bits (mode).coeffs[0]) >> 1;

rtx low[2], high[2];
int count;

if (CONST_INT_P (operands[2])(((enum rtx_code) (operands[2])->code) == CONST_INT))
  {
    split_double_mode (mode, operands, 2, low, high);
    count = INTVAL (operands[2])((operands[2])->u.hwint[0]) & (GET_MODE_BITSIZE (mode)((unsigned short) mode_to_bits (mode).coeffs[0]) - 1);

    if (count == GET_MODE_BITSIZE (mode)((unsigned short) mode_to_bits (mode).coeffs[0]) - 1)
{
 emit_move_insn (high[0], high[1]);
 emit_insn (gen_ashr3 (high[0], high[0],
		GEN_INT (half_width - 1)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (half_width - 1))));
 emit_move_insn (low[0], high[0]);

}
    else if (count >= half_width)
{
 emit_move_insn (low[0], high[1]);
 emit_move_insn (high[0], low[0]);
 emit_insn (gen_ashr3 (high[0], high[0],
		GEN_INT (half_width - 1)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (half_width - 1))));

 if (count > half_width)
   emit_insn (gen_ashr3 (low[0], low[0],
		  GEN_INT (count - half_width)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (count - half_width
))));
}
    else
{
 gen_shrd = mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) ? gen_x86_shrd : gen_x86_64_shrd;

 if (!rtx_equal_p (operands[0], operands[1]))
   emit_move_insn (operands[0], operands[1]);

 emit_insn (gen_shrd (low[0], high[0], GEN_INT (count)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (count))));
 emit_insn (gen_ashr3 (high[0], high[0], GEN_INT (count)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (count))));
}
  }
else
  {
    machine_mode half_mode;

    gen_shrd = mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) ? gen_x86_shrd : gen_x86_64_shrd;

   if (!rtx_equal_p (operands[0], operands[1]))
emit_move_insn (operands[0], operands[1]);

    split_double_mode (mode, operands, 1, low, high);
    half_mode = mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) ? SImode(scalar_int_mode ((scalar_int_mode::from_int) E_SImode)) : DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode));

    emit_insn (gen_shrd (low[0], high[0], operands[2]));
    emit_insn (gen_ashr3 (high[0], high[0], operands[2]));

    if (TARGET_CMOVE(ix86_arch_features[X86_ARCH_CMOV] || ((global_options.x_ix86_isa_flags
 & (1UL << 50)) != 0) || ((global_options.x_ix86_isa_flags
 & (1UL << 44)) != 0)) && scratch)
{
 emit_move_insn (scratch, high[0]);
 emit_insn (gen_ashr3 (scratch, scratch,
		GEN_INT (half_width - 1)gen_rtx_CONST_INT (((void) 0, E_VOIDmode), (half_width - 1))));
 emit_insn (gen_x86_shift_adj_1
     (half_mode, low[0], high[0], operands[2], scratch));
}
    else
emit_insn (gen_x86_shift_adj_3
   (half_mode, low[0], high[0], operands[2]));
  }
5701}

5703void
5704ix86_split_lshr (rtx *operands, rtx scratch, machine_mode mode)
5705{
rtx (*gen_lshr3)(rtx, rtx, rtx)
  = mode == DImode(scalar_int_mode ((scalar_int_mode::from_int) E_DImode)) ? gen_lshrsi3 : gen_lshrdi3;
rtx (*gen_shrd)(rtx, rtx, rtx);
int half_width = GET_MODE_BITSIZE (mode)((unsigned short) mode_to_bits (mode).coeffs[0]) >> 1;

rtx low[2], high[2];
int count;

if (CONST_INT_P (operands[2])(((enum rtx_code) (operands[2])->code) == CONST_INT))
  {
    split_double_mode (mode, operands, 2, low, high);
    count = INTVAL (operands[2])((operands[2])->u.hwint[0]) & (GET_MODE_BITSIZE (mode)((unsigned short) mode_to_bits (mode).coeffs[0]) - 1);

    if (count >= half_width)
{
 emit_move_insn (low[0], high[1]);
 ix86_expand_clear (high[0]);
5723