Bug Summary

File:build/gcc/ira-lives.c
Warning:line 947, column 4
Value stored to 'cl' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-unknown-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ira-lives.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model static -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -fno-split-dwarf-inlining -debugger-tuning=gdb -resource-dir /usr/lib64/clang/11.0.0 -D IN_GCC -D HAVE_CONFIG_H -I . -I . -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/. -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../include -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcpp/include -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libcody -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libdecnumber/bid -I ../libdecnumber -I /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/../libbacktrace -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/10/../../../../include/c++/10 -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/10/../../../../include/c++/10/x86_64-suse-linux -internal-isystem /usr/bin/../lib64/gcc/x86_64-suse-linux/10/../../../../include/c++/10/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib64/clang/11.0.0/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-narrowing -Wwrite-strings -Wno-error=format-diag -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings -fdeprecated-macro -fdebug-compilation-dir /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/gcc -ferror-limit 19 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=plist-html -analyzer-config silence-checkers=core.NullDereference -faddrsig -o /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/objdir/clang-static-analyzer/2021-01-16-135054-17580-1/report-70CsNA.plist -x c++ /home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c
1/* IRA processing allocno lives to build allocno live ranges.
2 Copyright (C) 2006-2021 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 3, or (at your option) any later
10version.
11
12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING3. If not see
19<http://www.gnu.org/licenses/>. */
20
21#include "config.h"
22#include "system.h"
23#include "coretypes.h"
24#include "backend.h"
25#include "target.h"
26#include "rtl.h"
27#include "predict.h"
28#include "df.h"
29#include "memmodel.h"
30#include "tm_p.h"
31#include "insn-config.h"
32#include "regs.h"
33#include "ira.h"
34#include "ira-int.h"
35#include "sparseset.h"
36#include "function-abi.h"
37
38/* The code in this file is similar to one in global but the code
39 works on the allocno basis and creates live ranges instead of
40 pseudo-register conflicts. */
41
42/* Program points are enumerated by numbers from range
43 0..IRA_MAX_POINT-1. There are approximately two times more program
44 points than insns. Program points are places in the program where
45 liveness info can be changed. In most general case (there are more
46 complicated cases too) some program points correspond to places
47 where input operand dies and other ones correspond to places where
48 output operands are born. */
49int ira_max_point;
50
51/* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
52 live ranges with given start/finish point. */
53live_range_t *ira_start_point_ranges, *ira_finish_point_ranges;
54
55/* Number of the current program point. */
56static int curr_point;
57
58/* Point where register pressure excess started or -1 if there is no
59 register pressure excess. Excess pressure for a register class at
60 some point means that there are more allocnos of given register
61 class living at the point than number of hard-registers of the
62 class available for the allocation. It is defined only for
63 pressure classes. */
64static int high_pressure_start_point[N_REG_CLASSES((int) LIM_REG_CLASSES)];
65
66/* Objects live at current point in the scan. */
67static sparseset objects_live;
68
69/* A temporary bitmap used in functions that wish to avoid visiting an allocno
70 multiple times. */
71static sparseset allocnos_processed;
72
73/* Set of hard regs (except eliminable ones) currently live. */
74static HARD_REG_SET hard_regs_live;
75
76/* The loop tree node corresponding to the current basic block. */
77static ira_loop_tree_node_t curr_bb_node;
78
79/* The number of the last processed call. */
80static int last_call_num;
81/* The number of last call at which given allocno was saved. */
82static int *allocno_saved_at_call;
83
84/* The value returned by ira_setup_alts for the current instruction;
85 i.e. the set of alternatives that we should consider to be likely
86 candidates during reloading. */
87static alternative_mask preferred_alternatives;
88
89/* If non-NULL, the source operand of a register to register copy for which
90 we should not add a conflict with the copy's destination operand. */
91static rtx ignore_reg_for_conflicts;
92
93/* Record hard register REGNO as now being live. */
94static void
95make_hard_regno_live (int regno)
96{
97 SET_HARD_REG_BIT (hard_regs_live, regno);
98}
99
100/* Process the definition of hard register REGNO. This updates
101 hard_regs_live and hard reg conflict information for living allocnos. */
102static void
103make_hard_regno_dead (int regno)
104{
105 unsigned int i;
106 EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)for (sparseset_iter_init (objects_live); sparseset_iter_p (objects_live
) && (((i) = sparseset_iter_elm (objects_live)) || 1)
; sparseset_iter_next (objects_live))
107 {
108 ira_object_t obj = ira_object_id_map[i];
109
110 if (ignore_reg_for_conflicts != NULL_RTX(rtx) 0
111 && REGNO (ignore_reg_for_conflicts)(rhs_regno(ignore_reg_for_conflicts))
112 == (unsigned int) ALLOCNO_REGNO (OBJECT_ALLOCNO (obj))((((obj)->allocno))->regno))
113 continue;
114
115 SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj)((obj)->conflict_hard_regs), regno);
116 SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)((obj)->total_conflict_hard_regs), regno);
117 }
118 CLEAR_HARD_REG_BIT (hard_regs_live, regno);
119}
120
121/* Record object OBJ as now being live. Set a bit for it in objects_live,
122 and start a new live range for it if necessary. */
123static void
124make_object_live (ira_object_t obj)
125{
126 sparseset_set_bit (objects_live, OBJECT_CONFLICT_ID (obj)((obj)->id));
127
128 live_range_t lr = OBJECT_LIVE_RANGES (obj)((obj)->live_ranges);
129 if (lr == NULLnullptr
130 || (lr->finish != curr_point && lr->finish + 1 != curr_point))
131 ira_add_live_range_to_object (obj, curr_point, -1);
132}
133
134/* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
135 associated with object OBJ. */
136static void
137update_allocno_pressure_excess_length (ira_object_t obj)
138{
139 ira_allocno_t a = OBJECT_ALLOCNO (obj)((obj)->allocno);
140 int start, i;
141 enum reg_class aclass, pclass, cl;
142 live_range_t p;
143
144 aclass = ALLOCNO_CLASS (a)((a)->aclass);
145 pclass = ira_pressure_class_translate(this_target_ira->x_ira_pressure_class_translate)[aclass];
146 for (i = 0;
147 (cl = ira_reg_class_super_classes(this_target_ira_int->x_ira_reg_class_super_classes)[pclass][i]) != LIM_REG_CLASSES;
148 i++)
149 {
150 if (! ira_reg_pressure_class_p(this_target_ira_int->x_ira_reg_pressure_class_p)[cl])
151 continue;
152 if (high_pressure_start_point[cl] < 0)
153 continue;
154 p = OBJECT_LIVE_RANGES (obj)((obj)->live_ranges);
155 ira_assert (p != NULL)((void)(!(p != nullptr) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 155, __FUNCTION__), 0 : 0))
;
156 start = (high_pressure_start_point[cl] > p->start
157 ? high_pressure_start_point[cl] : p->start);
158 ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a)((a)->excess_pressure_points_num) += curr_point - start + 1;
159 }
160}
161
162/* Process the definition of object OBJ, which is associated with allocno A.
163 This finishes the current live range for it. */
164static void
165make_object_dead (ira_object_t obj)
166{
167 live_range_t lr;
168 int regno;
169 int ignore_regno = -1;
170 int ignore_total_regno = -1;
171 int end_regno = -1;
172
173 sparseset_clear_bit (objects_live, OBJECT_CONFLICT_ID (obj)((obj)->id));
174
175 /* Check whether any part of IGNORE_REG_FOR_CONFLICTS already conflicts
176 with OBJ. */
177 if (ignore_reg_for_conflicts != NULL_RTX(rtx) 0
178 && REGNO (ignore_reg_for_conflicts)(rhs_regno(ignore_reg_for_conflicts)) < FIRST_PSEUDO_REGISTER76)
179 {
180 end_regno = END_REGNO (ignore_reg_for_conflicts);
181 ignore_regno = ignore_total_regno = REGNO (ignore_reg_for_conflicts)(rhs_regno(ignore_reg_for_conflicts));
182
183 for (regno = ignore_regno; regno < end_regno; regno++)
184 {
185 if (TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj)((obj)->conflict_hard_regs), regno))
186 ignore_regno = end_regno;
187 if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)((obj)->total_conflict_hard_regs), regno))
188 ignore_total_regno = end_regno;
189 }
190 }
191
192 OBJECT_CONFLICT_HARD_REGS (obj)((obj)->conflict_hard_regs) |= hard_regs_live;
193 OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)((obj)->total_conflict_hard_regs) |= hard_regs_live;
194
195 /* If IGNORE_REG_FOR_CONFLICTS did not already conflict with OBJ, make
196 sure it still doesn't. */
197 for (regno = ignore_regno; regno < end_regno; regno++)
198 CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj)((obj)->conflict_hard_regs), regno);
199 for (regno = ignore_total_regno; regno < end_regno; regno++)
200 CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)((obj)->total_conflict_hard_regs), regno);
201
202 lr = OBJECT_LIVE_RANGES (obj)((obj)->live_ranges);
203 ira_assert (lr != NULL)((void)(!(lr != nullptr) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 203, __FUNCTION__), 0 : 0))
;
204 lr->finish = curr_point;
205 update_allocno_pressure_excess_length (obj);
206}
207
208/* The current register pressures for each pressure class for the current
209 basic block. */
210static int curr_reg_pressure[N_REG_CLASSES((int) LIM_REG_CLASSES)];
211
212/* Record that register pressure for PCLASS increased by N registers.
213 Update the current register pressure, maximal register pressure for
214 the current BB and the start point of the register pressure
215 excess. */
216static void
217inc_register_pressure (enum reg_class pclass, int n)
218{
219 int i;
220 enum reg_class cl;
221
222 for (i = 0;
223 (cl = ira_reg_class_super_classes(this_target_ira_int->x_ira_reg_class_super_classes)[pclass][i]) != LIM_REG_CLASSES;
224 i++)
225 {
226 if (! ira_reg_pressure_class_p(this_target_ira_int->x_ira_reg_pressure_class_p)[cl])
227 continue;
228 curr_reg_pressure[cl] += n;
229 if (high_pressure_start_point[cl] < 0
230 && (curr_reg_pressure[cl] > ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num)[cl]))
231 high_pressure_start_point[cl] = curr_point;
232 if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
233 curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
234 }
235}
236
237/* Record that register pressure for PCLASS has decreased by NREGS
238 registers; update current register pressure, start point of the
239 register pressure excess, and register pressure excess length for
240 living allocnos. */
241
242static void
243dec_register_pressure (enum reg_class pclass, int nregs)
244{
245 int i;
246 unsigned int j;
247 enum reg_class cl;
248 bool set_p = false;
249
250 for (i = 0;
251 (cl = ira_reg_class_super_classes(this_target_ira_int->x_ira_reg_class_super_classes)[pclass][i]) != LIM_REG_CLASSES;
252 i++)
253 {
254 if (! ira_reg_pressure_class_p(this_target_ira_int->x_ira_reg_pressure_class_p)[cl])
255 continue;
256 curr_reg_pressure[cl] -= nregs;
257 ira_assert (curr_reg_pressure[cl] >= 0)((void)(!(curr_reg_pressure[cl] >= 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 257, __FUNCTION__), 0 : 0))
;
258 if (high_pressure_start_point[cl] >= 0
259 && curr_reg_pressure[cl] <= ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num)[cl])
260 set_p = true;
261 }
262 if (set_p)
263 {
264 EXECUTE_IF_SET_IN_SPARSESET (objects_live, j)for (sparseset_iter_init (objects_live); sparseset_iter_p (objects_live
) && (((j) = sparseset_iter_elm (objects_live)) || 1)
; sparseset_iter_next (objects_live))
265 update_allocno_pressure_excess_length (ira_object_id_map[j]);
266 for (i = 0;
267 (cl = ira_reg_class_super_classes(this_target_ira_int->x_ira_reg_class_super_classes)[pclass][i]) != LIM_REG_CLASSES;
268 i++)
269 {
270 if (! ira_reg_pressure_class_p(this_target_ira_int->x_ira_reg_pressure_class_p)[cl])
271 continue;
272 if (high_pressure_start_point[cl] >= 0
273 && curr_reg_pressure[cl] <= ira_class_hard_regs_num(this_target_ira->x_ira_class_hard_regs_num)[cl])
274 high_pressure_start_point[cl] = -1;
275 }
276 }
277}
278
279/* Determine from the objects_live bitmap whether REGNO is currently live,
280 and occupies only one object. Return false if we have no information. */
281static bool
282pseudo_regno_single_word_and_live_p (int regno)
283{
284 ira_allocno_t a = ira_curr_regno_allocno_map[regno];
285 ira_object_t obj;
286
287 if (a == NULLnullptr)
288 return false;
289 if (ALLOCNO_NUM_OBJECTS (a)((a)->num_objects) > 1)
290 return false;
291
292 obj = ALLOCNO_OBJECT (a, 0)((a)->objects[0]);
293
294 return sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)((obj)->id));
295}
296
297/* Mark the pseudo register REGNO as live. Update all information about
298 live ranges and register pressure. */
299static void
300mark_pseudo_regno_live (int regno)
301{
302 ira_allocno_t a = ira_curr_regno_allocno_map[regno];
303 enum reg_class pclass;
304 int i, n, nregs;
305
306 if (a == NULLnullptr)
307 return;
308
309 /* Invalidate because it is referenced. */
310 allocno_saved_at_call[ALLOCNO_NUM (a)((a)->num)] = 0;
311
312 n = ALLOCNO_NUM_OBJECTS (a)((a)->num_objects);
313 pclass = ira_pressure_class_translate(this_target_ira->x_ira_pressure_class_translate)[ALLOCNO_CLASS (a)((a)->aclass)];
314 nregs = ira_reg_class_max_nregs(this_target_ira->x_ira_reg_class_max_nregs)[ALLOCNO_CLASS (a)((a)->aclass)][ALLOCNO_MODE (a)((a)->mode)];
315 if (n > 1)
316 {
317 /* We track every subobject separately. */
318 gcc_assert (nregs == n)((void)(!(nregs == n) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 318, __FUNCTION__), 0 : 0))
;
319 nregs = 1;
320 }
321
322 for (i = 0; i < n; i++)
323 {
324 ira_object_t obj = ALLOCNO_OBJECT (a, i)((a)->objects[i]);
325
326 if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)((obj)->id)))
327 continue;
328
329 inc_register_pressure (pclass, nregs);
330 make_object_live (obj);
331 }
332}
333
334/* Like mark_pseudo_regno_live, but try to only mark one subword of
335 the pseudo as live. SUBWORD indicates which; a value of 0
336 indicates the low part. */
337static void
338mark_pseudo_regno_subword_live (int regno, int subword)
339{
340 ira_allocno_t a = ira_curr_regno_allocno_map[regno];
341 int n;
342 enum reg_class pclass;
343 ira_object_t obj;
344
345 if (a == NULLnullptr)
346 return;
347
348 /* Invalidate because it is referenced. */
349 allocno_saved_at_call[ALLOCNO_NUM (a)((a)->num)] = 0;
350
351 n = ALLOCNO_NUM_OBJECTS (a)((a)->num_objects);
352 if (n == 1)
353 {
354 mark_pseudo_regno_live (regno);
355 return;
356 }
357
358 pclass = ira_pressure_class_translate(this_target_ira->x_ira_pressure_class_translate)[ALLOCNO_CLASS (a)((a)->aclass)];
359 gcc_assert((void)(!(n == (this_target_ira->x_ira_reg_class_max_nregs
)[((a)->aclass)][((a)->mode)]) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 360, __FUNCTION__), 0 : 0))
360 (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)])((void)(!(n == (this_target_ira->x_ira_reg_class_max_nregs
)[((a)->aclass)][((a)->mode)]) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 360, __FUNCTION__), 0 : 0))
;
361 obj = ALLOCNO_OBJECT (a, subword)((a)->objects[subword]);
362
363 if (sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)((obj)->id)))
364 return;
365
366 inc_register_pressure (pclass, 1);
367 make_object_live (obj);
368}
369
370/* Mark the register REG as live. Store a 1 in hard_regs_live for
371 this register, record how many consecutive hardware registers it
372 actually needs. */
373static void
374mark_hard_reg_live (rtx reg)
375{
376 int regno = REGNO (reg)(rhs_regno(reg));
377
378 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs(this_target_ira->x_ira_no_alloc_regs), regno))
379 {
380 int last = END_REGNO (reg);
381 enum reg_class aclass, pclass;
382
383 while (regno < last)
384 {
385 if (! TEST_HARD_REG_BIT (hard_regs_live, regno)
386 && ! TEST_HARD_REG_BIT (eliminable_regset, regno))
387 {
388 aclass = ira_hard_regno_allocno_class(this_target_ira->x_ira_hard_regno_allocno_class)[regno];
389 pclass = ira_pressure_class_translate(this_target_ira->x_ira_pressure_class_translate)[aclass];
390 inc_register_pressure (pclass, 1);
391 make_hard_regno_live (regno);
392 }
393 regno++;
394 }
395 }
396}
397
398/* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
399 register number; ORIG_REG is the access in the insn, which may be a
400 subreg. */
401static void
402mark_pseudo_reg_live (rtx orig_reg, unsigned regno)
403{
404 if (read_modify_subreg_p (orig_reg))
405 {
406 mark_pseudo_regno_subword_live (regno,
407 subreg_lowpart_p (orig_reg) ? 0 : 1);
408 }
409 else
410 mark_pseudo_regno_live (regno);
411}
412
413/* Mark the register referenced by use or def REF as live. */
414static void
415mark_ref_live (df_ref ref)
416{
417 rtx reg = DF_REF_REG (ref)((ref)->base.reg);
418 rtx orig_reg = reg;
419
420 if (GET_CODE (reg)((enum rtx_code) (reg)->code) == SUBREG)
421 reg = SUBREG_REG (reg)(((reg)->u.fld[0]).rt_rtx);
422
423 if (REGNO (reg)(rhs_regno(reg)) >= FIRST_PSEUDO_REGISTER76)
424 mark_pseudo_reg_live (orig_reg, REGNO (reg)(rhs_regno(reg)));
425 else
426 mark_hard_reg_live (reg);
427}
428
429/* Mark the pseudo register REGNO as dead. Update all information about
430 live ranges and register pressure. */
431static void
432mark_pseudo_regno_dead (int regno)
433{
434 ira_allocno_t a = ira_curr_regno_allocno_map[regno];
435 int n, i, nregs;
436 enum reg_class cl;
437
438 if (a == NULLnullptr)
439 return;
440
441 /* Invalidate because it is referenced. */
442 allocno_saved_at_call[ALLOCNO_NUM (a)((a)->num)] = 0;
443
444 n = ALLOCNO_NUM_OBJECTS (a)((a)->num_objects);
445 cl = ira_pressure_class_translate(this_target_ira->x_ira_pressure_class_translate)[ALLOCNO_CLASS (a)((a)->aclass)];
446 nregs = ira_reg_class_max_nregs(this_target_ira->x_ira_reg_class_max_nregs)[ALLOCNO_CLASS (a)((a)->aclass)][ALLOCNO_MODE (a)((a)->mode)];
447 if (n > 1)
448 {
449 /* We track every subobject separately. */
450 gcc_assert (nregs == n)((void)(!(nregs == n) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 450, __FUNCTION__), 0 : 0))
;
451 nregs = 1;
452 }
453 for (i = 0; i < n; i++)
454 {
455 ira_object_t obj = ALLOCNO_OBJECT (a, i)((a)->objects[i]);
456 if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)((obj)->id)))
457 continue;
458
459 dec_register_pressure (cl, nregs);
460 make_object_dead (obj);
461 }
462}
463
464/* Like mark_pseudo_regno_dead, but called when we know that only part of the
465 register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
466static void
467mark_pseudo_regno_subword_dead (int regno, int subword)
468{
469 ira_allocno_t a = ira_curr_regno_allocno_map[regno];
470 int n;
471 enum reg_class cl;
472 ira_object_t obj;
473
474 if (a == NULLnullptr)
475 return;
476
477 /* Invalidate because it is referenced. */
478 allocno_saved_at_call[ALLOCNO_NUM (a)((a)->num)] = 0;
479
480 n = ALLOCNO_NUM_OBJECTS (a)((a)->num_objects);
481 if (n == 1)
482 /* The allocno as a whole doesn't die in this case. */
483 return;
484
485 cl = ira_pressure_class_translate(this_target_ira->x_ira_pressure_class_translate)[ALLOCNO_CLASS (a)((a)->aclass)];
486 gcc_assert((void)(!(n == (this_target_ira->x_ira_reg_class_max_nregs
)[((a)->aclass)][((a)->mode)]) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 487, __FUNCTION__), 0 : 0))
487 (n == ira_reg_class_max_nregs[ALLOCNO_CLASS (a)][ALLOCNO_MODE (a)])((void)(!(n == (this_target_ira->x_ira_reg_class_max_nregs
)[((a)->aclass)][((a)->mode)]) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 487, __FUNCTION__), 0 : 0))
;
488
489 obj = ALLOCNO_OBJECT (a, subword)((a)->objects[subword]);
490 if (!sparseset_bit_p (objects_live, OBJECT_CONFLICT_ID (obj)((obj)->id)))
491 return;
492
493 dec_register_pressure (cl, 1);
494 make_object_dead (obj);
495}
496
497/* Process the definition of hard register REG. This updates hard_regs_live
498 and hard reg conflict information for living allocnos. */
499static void
500mark_hard_reg_dead (rtx reg)
501{
502 int regno = REGNO (reg)(rhs_regno(reg));
503
504 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs(this_target_ira->x_ira_no_alloc_regs), regno))
505 {
506 int last = END_REGNO (reg);
507 enum reg_class aclass, pclass;
508
509 while (regno < last)
510 {
511 if (TEST_HARD_REG_BIT (hard_regs_live, regno))
512 {
513 aclass = ira_hard_regno_allocno_class(this_target_ira->x_ira_hard_regno_allocno_class)[regno];
514 pclass = ira_pressure_class_translate(this_target_ira->x_ira_pressure_class_translate)[aclass];
515 dec_register_pressure (pclass, 1);
516 make_hard_regno_dead (regno);
517 }
518 regno++;
519 }
520 }
521}
522
523/* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
524 register number; ORIG_REG is the access in the insn, which may be a
525 subreg. */
526static void
527mark_pseudo_reg_dead (rtx orig_reg, unsigned regno)
528{
529 if (read_modify_subreg_p (orig_reg))
530 {
531 mark_pseudo_regno_subword_dead (regno,
532 subreg_lowpart_p (orig_reg) ? 0 : 1);
533 }
534 else
535 mark_pseudo_regno_dead (regno);
536}
537
538/* Mark the register referenced by definition DEF as dead, if the
539 definition is a total one. */
540static void
541mark_ref_dead (df_ref def)
542{
543 rtx reg = DF_REF_REG (def)((def)->base.reg);
544 rtx orig_reg = reg;
545
546 if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL)((((def)->base.flags) & (DF_REF_CONDITIONAL)) != 0))
547 return;
548
549 if (GET_CODE (reg)((enum rtx_code) (reg)->code) == SUBREG)
550 reg = SUBREG_REG (reg)(((reg)->u.fld[0]).rt_rtx);
551
552 if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)((((def)->base.flags) & (DF_REF_PARTIAL)) != 0)
553 && (GET_CODE (orig_reg)((enum rtx_code) (orig_reg)->code) != SUBREG
554 || REGNO (reg)(rhs_regno(reg)) < FIRST_PSEUDO_REGISTER76
555 || !read_modify_subreg_p (orig_reg)))
556 return;
557
558 if (REGNO (reg)(rhs_regno(reg)) >= FIRST_PSEUDO_REGISTER76)
559 mark_pseudo_reg_dead (orig_reg, REGNO (reg)(rhs_regno(reg)));
560 else
561 mark_hard_reg_dead (reg);
562}
563
564/* If REG is a pseudo or a subreg of it, and the class of its allocno
565 intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
566 rtx actually accessed, it may be identical to DREG or a subreg of it.
567 Advance the current program point before making the conflict if
568 ADVANCE_P. Return TRUE if we will need to advance the current
569 program point. */
570static bool
571make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
572 bool advance_p)
573{
574 rtx orig_reg = reg;
575 ira_allocno_t a;
576
577 if (GET_CODE (reg)((enum rtx_code) (reg)->code) == SUBREG)
578 reg = SUBREG_REG (reg)(((reg)->u.fld[0]).rt_rtx);
579
580 if (! REG_P (reg)(((enum rtx_code) (reg)->code) == REG) || REGNO (reg)(rhs_regno(reg)) < FIRST_PSEUDO_REGISTER76)
581 return advance_p;
582
583 a = ira_curr_regno_allocno_map[REGNO (reg)(rhs_regno(reg))];
584 if (! reg_classes_intersect_p (cl, ALLOCNO_CLASS (a)((a)->aclass)))
585 return advance_p;
586
587 if (advance_p)
588 curr_point++;
589
590 mark_pseudo_reg_live (orig_reg, REGNO (reg)(rhs_regno(reg)));
591 mark_pseudo_reg_live (orig_dreg, REGNO (dreg)(rhs_regno(dreg)));
592 mark_pseudo_reg_dead (orig_reg, REGNO (reg)(rhs_regno(reg)));
593 mark_pseudo_reg_dead (orig_dreg, REGNO (dreg)(rhs_regno(dreg)));
594
595 return false;
596}
597
598/* Check and make if necessary conflicts for pseudo DREG of class
599 DEF_CL of the current insn with input operand USE of class USE_CL.
600 ORIG_DREG is the rtx actually accessed, it may be identical to
601 DREG or a subreg of it. Advance the current program point before
602 making the conflict if ADVANCE_P. Return TRUE if we will need to
603 advance the current program point. */
604static bool
605check_and_make_def_use_conflict (rtx dreg, rtx orig_dreg,
606 enum reg_class def_cl, int use,
607 enum reg_class use_cl, bool advance_p)
608{
609 if (! reg_classes_intersect_p (def_cl, use_cl))
610 return advance_p;
611
612 advance_p = make_pseudo_conflict (recog_data.operand[use],
613 use_cl, dreg, orig_dreg, advance_p);
614
615 /* Reload may end up swapping commutative operands, so you
616 have to take both orderings into account. The
617 constraints for the two operands can be completely
618 different. (Indeed, if the constraints for the two
619 operands are the same for all alternatives, there's no
620 point marking them as commutative.) */
621 if (use < recog_data.n_operands - 1
622 && recog_data.constraints[use][0] == '%')
623 advance_p
624 = make_pseudo_conflict (recog_data.operand[use + 1],
625 use_cl, dreg, orig_dreg, advance_p);
626 if (use >= 1
627 && recog_data.constraints[use - 1][0] == '%')
628 advance_p
629 = make_pseudo_conflict (recog_data.operand[use - 1],
630 use_cl, dreg, orig_dreg, advance_p);
631 return advance_p;
632}
633
634/* Check and make if necessary conflicts for definition DEF of class
635 DEF_CL of the current insn with input operands. Process only
636 constraints of alternative ALT.
637
638 One of three things is true when this function is called:
639
640 (1) DEF is an earlyclobber for alternative ALT. Input operands then
641 conflict with DEF in ALT unless they explicitly match DEF via 0-9
642 constraints.
643
644 (2) DEF matches (via 0-9 constraints) an operand that is an
645 earlyclobber for alternative ALT. Other input operands then
646 conflict with DEF in ALT.
647
648 (3) [FOR_TIE_P] Some input operand X matches DEF for alternative ALT.
649 Input operands with a different value from X then conflict with
650 DEF in ALT.
651
652 However, there's still a judgement call to make when deciding
653 whether a conflict in ALT is important enough to be reflected
654 in the pan-alternative allocno conflict set. */
655static void
656check_and_make_def_conflict (int alt, int def, enum reg_class def_cl,
657 bool for_tie_p)
658{
659 int use, use_match;
660 ira_allocno_t a;
661 enum reg_class use_cl, acl;
662 bool advance_p;
663 rtx dreg = recog_data.operand[def];
664 rtx orig_dreg = dreg;
665
666 if (def_cl == NO_REGS)
667 return;
668
669 if (GET_CODE (dreg)((enum rtx_code) (dreg)->code) == SUBREG)
670 dreg = SUBREG_REG (dreg)(((dreg)->u.fld[0]).rt_rtx);
671
672 if (! REG_P (dreg)(((enum rtx_code) (dreg)->code) == REG) || REGNO (dreg)(rhs_regno(dreg)) < FIRST_PSEUDO_REGISTER76)
673 return;
674
675 a = ira_curr_regno_allocno_map[REGNO (dreg)(rhs_regno(dreg))];
676 acl = ALLOCNO_CLASS (a)((a)->aclass);
677 if (! reg_classes_intersect_p (acl, def_cl))
678 return;
679
680 advance_p = true;
681
682 int n_operands = recog_data.n_operands;
683 const operand_alternative *op_alt = &recog_op_alt[alt * n_operands];
684 for (use = 0; use < n_operands; use++)
685 {
686 int alt1;
687
688 if (use == def || recog_data.operand_type[use] == OP_OUT)
689 continue;
690
691 /* An earlyclobber on DEF doesn't apply to an input operand X if X
692 explicitly matches DEF, but it applies to other input operands
693 even if they happen to be the same value as X.
694
695 In contrast, if an input operand X is tied to a non-earlyclobber
696 DEF, there's no conflict with other input operands that have the
697 same value as X. */
698 if (op_alt[use].matches == def
699 || (for_tie_p
700 && rtx_equal_p (recog_data.operand[use],
701 recog_data.operand[op_alt[def].matched])))
702 continue;
703
704 if (op_alt[use].anything_ok)
705 use_cl = ALL_REGS;
706 else
707 use_cl = op_alt[use].cl;
708 if (use_cl == NO_REGS)
709 continue;
710
711 /* If DEF is simply a tied operand, ignore cases in which this
712 alternative requires USE to have a likely-spilled class.
713 Adding a conflict would just constrain USE further if DEF
714 happens to be allocated first. */
715 if (for_tie_p && targetm.class_likely_spilled_p (use_cl))
716 continue;
717
718 /* If there's any alternative that allows USE to match DEF, do not
719 record a conflict. If that causes us to create an invalid
720 instruction due to the earlyclobber, reload must fix it up.
721
722 Likewise, if we're treating a tied DEF like a partial earlyclobber,
723 do not record a conflict if there's another alternative in which
724 DEF is neither tied nor earlyclobber. */
725 for (alt1 = 0; alt1 < recog_data.n_alternatives; alt1++)
726 {
727 if (!TEST_BIT (preferred_alternatives, alt1)(((preferred_alternatives) >> (alt1)) & 1))
728 continue;
729 const operand_alternative *op_alt1
730 = &recog_op_alt[alt1 * n_operands];
731 if (op_alt1[use].matches == def
732 || (use < n_operands - 1
733 && recog_data.constraints[use][0] == '%'
734 && op_alt1[use + 1].matches == def)
735 || (use >= 1
736 && recog_data.constraints[use - 1][0] == '%'
737 && op_alt1[use - 1].matches == def))
738 break;
739 if (for_tie_p
740 && !op_alt1[def].earlyclobber
741 && op_alt1[def].matched < 0
742 && alternative_class (op_alt1, def) != NO_REGS
743 && alternative_class (op_alt1, use) != NO_REGS)
744 break;
745 }
746
747 if (alt1 < recog_data.n_alternatives)
748 continue;
749
750 advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
751 use, use_cl, advance_p);
752
753 if ((use_match = op_alt[use].matches) >= 0)
754 {
755 gcc_checking_assert (use_match != def)((void)(!(use_match != def) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 755, __FUNCTION__), 0 : 0))
;
756
757 if (op_alt[use_match].anything_ok)
758 use_cl = ALL_REGS;
759 else
760 use_cl = op_alt[use_match].cl;
761 advance_p = check_and_make_def_use_conflict (dreg, orig_dreg, def_cl,
762 use, use_cl, advance_p);
763 }
764 }
765}
766
767/* Make conflicts of early clobber pseudo registers of the current
768 insn with its inputs. Avoid introducing unnecessary conflicts by
769 checking classes of the constraints and pseudos because otherwise
770 significant code degradation is possible for some targets.
771
772 For these purposes, tying an input to an output makes that output act
773 like an earlyclobber for inputs with a different value, since the output
774 register then has a predetermined purpose on input to the instruction. */
775static void
776make_early_clobber_and_input_conflicts (void)
777{
778 int alt;
779 int def, def_match;
780 enum reg_class def_cl;
781
782 int n_alternatives = recog_data.n_alternatives;
783 int n_operands = recog_data.n_operands;
784 const operand_alternative *op_alt = recog_op_alt;
785 for (alt = 0; alt < n_alternatives; alt++, op_alt += n_operands)
786 if (TEST_BIT (preferred_alternatives, alt)(((preferred_alternatives) >> (alt)) & 1))
787 for (def = 0; def < n_operands; def++)
788 {
789 if (op_alt[def].anything_ok)
790 def_cl = ALL_REGS;
791 else
792 def_cl = op_alt[def].cl;
793 if (def_cl != NO_REGS)
794 {
795 if (op_alt[def].earlyclobber)
796 check_and_make_def_conflict (alt, def, def_cl, false);
797 else if (op_alt[def].matched >= 0
798 && !targetm.class_likely_spilled_p (def_cl))
799 check_and_make_def_conflict (alt, def, def_cl, true);
800 }
801
802 if ((def_match = op_alt[def].matches) >= 0
803 && (op_alt[def_match].earlyclobber
804 || op_alt[def].earlyclobber))
805 {
806 if (op_alt[def_match].anything_ok)
807 def_cl = ALL_REGS;
808 else
809 def_cl = op_alt[def_match].cl;
810 check_and_make_def_conflict (alt, def, def_cl, false);
811 }
812 }
813}
814
815/* Mark early clobber hard registers of the current INSN as live (if
816 LIVE_P) or dead. Return true if there are such registers. */
817static bool
818mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p)
819{
820 df_ref def;
821 bool set_p = false;
822
823 FOR_EACH_INSN_DEF (def, insn)for (def = (((df->insns[(INSN_UID (insn))]))->defs); def
; def = ((def)->base.next_loc))
824 if (DF_REF_FLAGS_IS_SET (def, DF_REF_MUST_CLOBBER)((((def)->base.flags) & (DF_REF_MUST_CLOBBER)) != 0))
825 {
826 rtx dreg = DF_REF_REG (def)((def)->base.reg);
827
828 if (GET_CODE (dreg)((enum rtx_code) (dreg)->code) == SUBREG)
829 dreg = SUBREG_REG (dreg)(((dreg)->u.fld[0]).rt_rtx);
830 if (! REG_P (dreg)(((enum rtx_code) (dreg)->code) == REG) || REGNO (dreg)(rhs_regno(dreg)) >= FIRST_PSEUDO_REGISTER76)
831 continue;
832
833 /* Hard register clobbers are believed to be early clobber
834 because there is no way to say that non-operand hard
835 register clobbers are not early ones. */
836 if (live_p)
837 mark_ref_live (def);
838 else
839 mark_ref_dead (def);
840 set_p = true;
841 }
842
843 return set_p;
844}
845
846/* Checks that CONSTRAINTS permits to use only one hard register. If
847 it is so, the function returns the class of the hard register.
848 Otherwise it returns NO_REGS. */
849static enum reg_class
850single_reg_class (const char *constraints, rtx op, rtx equiv_const)
851{
852 int c;
853 enum reg_class cl, next_cl;
854 enum constraint_num cn;
855
856 cl = NO_REGS;
857 alternative_mask preferred = preferred_alternatives;
858 for (; (c = *constraints); constraints += CONSTRAINT_LEN (c, constraints)insn_constraint_len (c,constraints))
859 if (c == '#')
860 preferred &= ~ALTERNATIVE_BIT (0)((alternative_mask) 1 << (0));
861 else if (c == ',')
862 preferred >>= 1;
863 else if (preferred & 1)
864 switch (c)
865 {
866 case 'g':
867 return NO_REGS;
868
869 default:
870 /* ??? Is this the best way to handle memory constraints? */
871 cn = lookup_constraint (constraints);
872 if (insn_extra_memory_constraint (cn)
873 || insn_extra_special_memory_constraint (cn)
874 || insn_extra_address_constraint (cn))
875 return NO_REGS;
876 if (constraint_satisfied_p (op, cn)
877 || (equiv_const != NULL_RTX(rtx) 0
878 && CONSTANT_P (equiv_const)((rtx_class[(int) (((enum rtx_code) (equiv_const)->code))]
) == RTX_CONST_OBJ)
879 && constraint_satisfied_p (equiv_const, cn)))
880 return NO_REGS;
881 next_cl = reg_class_for_constraint (cn);
882 if (next_cl == NO_REGS)
883 break;
884 if (cl == NO_REGS
885 ? ira_class_singleton(this_target_ira->x_ira_class_singleton)[next_cl][GET_MODE (op)((machine_mode) (op)->mode)] < 0
886 : (ira_class_singleton(this_target_ira->x_ira_class_singleton)[cl][GET_MODE (op)((machine_mode) (op)->mode)]
887 != ira_class_singleton(this_target_ira->x_ira_class_singleton)[next_cl][GET_MODE (op)((machine_mode) (op)->mode)]))
888 return NO_REGS;
889 cl = next_cl;
890 break;
891
892 case '0': case '1': case '2': case '3': case '4':
893 case '5': case '6': case '7': case '8': case '9':
894 next_cl
895 = single_reg_class (recog_data.constraints[c - '0'],
896 recog_data.operand[c - '0'], NULL_RTX(rtx) 0);
897 if (cl == NO_REGS
898 ? ira_class_singleton(this_target_ira->x_ira_class_singleton)[next_cl][GET_MODE (op)((machine_mode) (op)->mode)] < 0
899 : (ira_class_singleton(this_target_ira->x_ira_class_singleton)[cl][GET_MODE (op)((machine_mode) (op)->mode)]
900 != ira_class_singleton(this_target_ira->x_ira_class_singleton)[next_cl][GET_MODE (op)((machine_mode) (op)->mode)]))
901 return NO_REGS;
902 cl = next_cl;
903 break;
904 }
905 return cl;
906}
907
908/* The function checks that operand OP_NUM of the current insn can use
909 only one hard register. If it is so, the function returns the
910 class of the hard register. Otherwise it returns NO_REGS. */
911static enum reg_class
912single_reg_operand_class (int op_num)
913{
914 if (op_num < 0 || recog_data.n_alternatives == 0)
915 return NO_REGS;
916 return single_reg_class (recog_data.constraints[op_num],
917 recog_data.operand[op_num], NULL_RTX(rtx) 0);
918}
919
920/* The function sets up hard register set *SET to hard registers which
921 might be used by insn reloads because the constraints are too
922 strict. */
923void
924ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set,
925 alternative_mask preferred)
926{
927 int i, c, regno = 0;
928 enum reg_class cl;
929 rtx op;
930 machine_mode mode;
931
932 CLEAR_HARD_REG_SET (*set);
933 for (i = 0; i < recog_data.n_operands; i++)
934 {
935 op = recog_data.operand[i];
936
937 if (GET_CODE (op)((enum rtx_code) (op)->code) == SUBREG)
938 op = SUBREG_REG (op)(((op)->u.fld[0]).rt_rtx);
939
940 if (GET_CODE (op)((enum rtx_code) (op)->code) == SCRATCH
941 || (REG_P (op)(((enum rtx_code) (op)->code) == REG) && (regno = REGNO (op)(rhs_regno(op))) >= FIRST_PSEUDO_REGISTER76))
942 {
943 const char *p = recog_data.constraints[i];
944
945 mode = (GET_CODE (op)((enum rtx_code) (op)->code) == SCRATCH
946 ? GET_MODE (op)((machine_mode) (op)->mode) : PSEUDO_REGNO_MODE (regno)((machine_mode) (regno_reg_rtx[regno])->mode));
947 cl = NO_REGS;
Value stored to 'cl' is never read
948 for (; (c = *p); p += CONSTRAINT_LEN (c, p)insn_constraint_len (c,p))
949 if (c == '#')
950 preferred &= ~ALTERNATIVE_BIT (0)((alternative_mask) 1 << (0));
951 else if (c == ',')
952 preferred >>= 1;
953 else if (preferred & 1)
954 {
955 cl = reg_class_for_constraint (lookup_constraint (p));
956 if (cl != NO_REGS)
957 {
958 /* There is no register pressure problem if all of the
959 regs in this class are fixed. */
960 int regno = ira_class_singleton(this_target_ira->x_ira_class_singleton)[cl][mode];
961 if (regno >= 0)
962 add_to_hard_reg_set (set, mode, regno);
963 }
964 }
965 }
966 }
967}
968/* Processes input operands, if IN_P, or output operands otherwise of
969 the current insn with FREQ to find allocno which can use only one
970 hard register and makes other currently living allocnos conflicting
971 with the hard register. */
972static void
973process_single_reg_class_operands (bool in_p, int freq)
974{
975 int i, regno;
976 unsigned int px;
977 enum reg_class cl;
978 rtx operand;
979 ira_allocno_t operand_a, a;
980
981 for (i = 0; i < recog_data.n_operands; i++)
982 {
983 operand = recog_data.operand[i];
984 if (in_p && recog_data.operand_type[i] != OP_IN
985 && recog_data.operand_type[i] != OP_INOUT)
986 continue;
987 if (! in_p && recog_data.operand_type[i] != OP_OUT
988 && recog_data.operand_type[i] != OP_INOUT)
989 continue;
990 cl = single_reg_operand_class (i);
991 if (cl == NO_REGS)
992 continue;
993
994 operand_a = NULLnullptr;
995
996 if (GET_CODE (operand)((enum rtx_code) (operand)->code) == SUBREG)
997 operand = SUBREG_REG (operand)(((operand)->u.fld[0]).rt_rtx);
998
999 if (REG_P (operand)(((enum rtx_code) (operand)->code) == REG)
1000 && (regno = REGNO (operand)(rhs_regno(operand))) >= FIRST_PSEUDO_REGISTER76)
1001 {
1002 enum reg_class aclass;
1003
1004 operand_a = ira_curr_regno_allocno_map[regno];
1005 aclass = ALLOCNO_CLASS (operand_a)((operand_a)->aclass);
1006 if (ira_class_subset_p(this_target_ira->x_ira_class_subset_p)[cl][aclass])
1007 {
1008 /* View the desired allocation of OPERAND as:
1009
1010 (REG:YMODE YREGNO),
1011
1012 a simplification of:
1013
1014 (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
1015 machine_mode ymode, xmode;
1016 int xregno, yregno;
1017 poly_int64 offset;
1018
1019 xmode = recog_data.operand_mode[i];
1020 xregno = ira_class_singleton(this_target_ira->x_ira_class_singleton)[cl][xmode];
1021 gcc_assert (xregno >= 0)((void)(!(xregno >= 0) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 1021, __FUNCTION__), 0 : 0))
;
1022 ymode = ALLOCNO_MODE (operand_a)((operand_a)->mode);
1023 offset = subreg_lowpart_offset (ymode, xmode);
1024 yregno = simplify_subreg_regno (xregno, xmode, offset, ymode);
1025 if (yregno >= 0
1026 && ira_class_hard_reg_index(this_target_ira_int->x_ira_class_hard_reg_index)[aclass][yregno] >= 0)
1027 {
1028 int cost;
1029
1030 ira_allocate_and_set_costs
1031 (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)((operand_a)->conflict_hard_reg_costs),
1032 aclass, 0);
1033 ira_init_register_move_cost_if_necessary (xmode);
1034 cost = freq * (in_p
1035 ? ira_register_move_cost(this_target_ira_int->x_ira_register_move_cost)[xmode][aclass][cl]
1036 : ira_register_move_cost(this_target_ira_int->x_ira_register_move_cost)[xmode][cl][aclass]);
1037 ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a)((operand_a)->conflict_hard_reg_costs)
1038 [ira_class_hard_reg_index(this_target_ira_int->x_ira_class_hard_reg_index)[aclass][yregno]] -= cost;
1039 }
1040 }
1041 }
1042
1043 EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)for (sparseset_iter_init (objects_live); sparseset_iter_p (objects_live
) && (((px) = sparseset_iter_elm (objects_live)) || 1
); sparseset_iter_next (objects_live))
1044 {
1045 ira_object_t obj = ira_object_id_map[px];
1046 a = OBJECT_ALLOCNO (obj)((obj)->allocno);
1047 if (a != operand_a)
1048 {
1049 /* We could increase costs of A instead of making it
1050 conflicting with the hard register. But it works worse
1051 because it will be spilled in reload in anyway. */
1052 OBJECT_CONFLICT_HARD_REGS (obj)((obj)->conflict_hard_regs) |= reg_class_contents(this_target_hard_regs->x_reg_class_contents)[cl];
1053 OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)((obj)->total_conflict_hard_regs) |= reg_class_contents(this_target_hard_regs->x_reg_class_contents)[cl];
1054 }
1055 }
1056 }
1057}
1058
1059/* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
1060 we find a SET rtx that we can use to deduce that a register can be cheaply
1061 caller-saved. Return such a register, or NULL_RTX if none is found. */
1062static rtx
1063find_call_crossed_cheap_reg (rtx_insn *insn)
1064{
1065 rtx cheap_reg = NULL_RTX(rtx) 0;
1066 rtx exp = CALL_INSN_FUNCTION_USAGE (insn)(((insn)->u.fld[7]).rt_rtx);
1067
1068 while (exp != NULLnullptr)
1069 {
1070 rtx x = XEXP (exp, 0)(((exp)->u.fld[0]).rt_rtx);
1071 if (GET_CODE (x)((enum rtx_code) (x)->code) == SET)
1072 {
1073 exp = x;
1074 break;
1075 }
1076 exp = XEXP (exp, 1)(((exp)->u.fld[1]).rt_rtx);
1077 }
1078 if (exp != NULLnullptr)
1079 {
1080 basic_block bb = BLOCK_FOR_INSN (insn);
1081 rtx reg = SET_SRC (exp)(((exp)->u.fld[1]).rt_rtx);
1082 rtx_insn *prev = PREV_INSN (insn);
1083 while (prev && !(INSN_P (prev)(((((enum rtx_code) (prev)->code) == INSN) || (((enum rtx_code
) (prev)->code) == JUMP_INSN) || (((enum rtx_code) (prev)->
code) == CALL_INSN)) || (((enum rtx_code) (prev)->code) ==
DEBUG_INSN))
1084 && BLOCK_FOR_INSN (prev) != bb))
1085 {
1086 if (NONDEBUG_INSN_P (prev)((((enum rtx_code) (prev)->code) == INSN) || (((enum rtx_code
) (prev)->code) == JUMP_INSN) || (((enum rtx_code) (prev)->
code) == CALL_INSN))
)
1087 {
1088 rtx set = single_set (prev);
1089
1090 if (set && rtx_equal_p (SET_DEST (set)(((set)->u.fld[0]).rt_rtx), reg))
1091 {
1092 rtx src = SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
1093 if (!REG_P (src)(((enum rtx_code) (src)->code) == REG) || HARD_REGISTER_P (src)((((rhs_regno(src))) < 76))
1094 || !pseudo_regno_single_word_and_live_p (REGNO (src)(rhs_regno(src))))
1095 break;
1096 if (!modified_between_p (src, prev, insn))
1097 cheap_reg = src;
1098 break;
1099 }
1100 if (set && rtx_equal_p (SET_SRC (set)(((set)->u.fld[1]).rt_rtx), reg))
1101 {
1102 rtx dest = SET_DEST (set)(((set)->u.fld[0]).rt_rtx);
1103 if (!REG_P (dest)(((enum rtx_code) (dest)->code) == REG) || HARD_REGISTER_P (dest)((((rhs_regno(dest))) < 76))
1104 || !pseudo_regno_single_word_and_live_p (REGNO (dest)(rhs_regno(dest))))
1105 break;
1106 if (!modified_between_p (dest, prev, insn))
1107 cheap_reg = dest;
1108 break;
1109 }
1110
1111 if (reg_set_p (reg, prev))
1112 break;
1113 }
1114 prev = PREV_INSN (prev);
1115 }
1116 }
1117 return cheap_reg;
1118}
1119
1120/* Determine whether INSN is a register to register copy of the type where
1121 we do not need to make the source and destiniation registers conflict.
1122 If this is a copy instruction, then return the source reg. Otherwise,
1123 return NULL_RTX. */
1124rtx
1125non_conflicting_reg_copy_p (rtx_insn *insn)
1126{
1127 /* Reload has issues with overlapping pseudos being assigned to the
1128 same hard register, so don't allow it. See PR87600 for details. */
1129 if (!targetm.lra_p ())
1130 return NULL_RTX(rtx) 0;
1131
1132 rtx set = single_set (insn);
1133
1134 /* Disallow anything other than a simple register to register copy
1135 that has no side effects. */
1136 if (set == NULL_RTX(rtx) 0
1137 || !REG_P (SET_DEST (set))(((enum rtx_code) ((((set)->u.fld[0]).rt_rtx))->code) ==
REG)
1138 || !REG_P (SET_SRC (set))(((enum rtx_code) ((((set)->u.fld[1]).rt_rtx))->code) ==
REG)
1139 || side_effects_p (set))
1140 return NULL_RTX(rtx) 0;
1141
1142 int dst_regno = REGNO (SET_DEST (set))(rhs_regno((((set)->u.fld[0]).rt_rtx)));
1143 int src_regno = REGNO (SET_SRC (set))(rhs_regno((((set)->u.fld[1]).rt_rtx)));
1144 machine_mode mode = GET_MODE (SET_DEST (set))((machine_mode) ((((set)->u.fld[0]).rt_rtx))->mode);
1145
1146 /* By definition, a register does not conflict with itself, therefore we
1147 do not have to handle it specially. Returning NULL_RTX now, helps
1148 simplify the callers of this function. */
1149 if (dst_regno == src_regno)
1150 return NULL_RTX(rtx) 0;
1151
1152 /* Computing conflicts for register pairs is difficult to get right, so
1153 for now, disallow it. */
1154 if ((HARD_REGISTER_NUM_P (dst_regno)((dst_regno) < 76)
1155 && hard_regno_nregs (dst_regno, mode) != 1)
1156 || (HARD_REGISTER_NUM_P (src_regno)((src_regno) < 76)
1157 && hard_regno_nregs (src_regno, mode) != 1))
1158 return NULL_RTX(rtx) 0;
1159
1160 return SET_SRC (set)(((set)->u.fld[1]).rt_rtx);
1161}
1162
1163#ifdef EH_RETURN_DATA_REGNO
1164
1165/* Add EH return hard registers as conflict hard registers to allocnos
1166 living at end of BB. For most allocnos it is already done in
1167 process_bb_node_lives when we processing input edges but it does
1168 not work when and EH edge is edge out of the current region. This
1169 function covers such out of region edges. */
1170static void
1171process_out_of_region_eh_regs (basic_block bb)
1172{
1173 edge e;
1174 edge_iterator ei;
1175 unsigned int i;
1176 bitmap_iterator bi;
1177 bool eh_p = false;
1178
1179 FOR_EACH_EDGE (e, ei, bb->succs)for ((ei) = ei_start_1 (&((bb->succs))); ei_cond ((ei)
, &(e)); ei_next (&(ei)))
1180 if ((e->flags & EDGE_EH)
1181 && IRA_BB_NODE (e->dest)__extension__ (({ ira_loop_tree_node_t _node = (&ira_bb_nodes
[(e->dest)->index]); if (_node->children != nullptr ||
_node->loop != nullptr || _node->bb == nullptr) { fprintf
(stderr, "\n%s: %d: error in %s: it is not a block node\n", "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 1181, __FUNCTION__); (fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 1181, __FUNCTION__)); } _node; }))
->parent != IRA_BB_NODE (bb)__extension__ (({ ira_loop_tree_node_t _node = (&ira_bb_nodes
[(bb)->index]); if (_node->children != nullptr || _node
->loop != nullptr || _node->bb == nullptr) { fprintf (stderr
, "\n%s: %d: error in %s: it is not a block node\n", "/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 1181, __FUNCTION__); (fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 1181, __FUNCTION__)); } _node; }))
->parent)
1182 eh_p = true;
1183
1184 if (! eh_p)
1185 return;
1186
1187 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), FIRST_PSEUDO_REGISTER, i, bi)for (bmp_iter_set_init (&(bi), (df_get_live_out (bb)), (76
), &(i)); bmp_iter_set (&(bi), &(i)); bmp_iter_next
(&(bi), &(i)))
1188 {
1189 ira_allocno_t a = ira_curr_regno_allocno_map[i];
1190 for (int n = ALLOCNO_NUM_OBJECTS (a)((a)->num_objects) - 1; n >= 0; n--)
1191 {
1192 ira_object_t obj = ALLOCNO_OBJECT (a, n)((a)->objects[n]);
1193 for (int k = 0; ; k++)
1194 {
1195 unsigned int regno = EH_RETURN_DATA_REGNO (k)((k) <= 1 ? (k) : (~(unsigned int) 0));
1196 if (regno == INVALID_REGNUM(~(unsigned int) 0))
1197 break;
1198 SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj)((obj)->conflict_hard_regs), regno);
1199 SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)((obj)->total_conflict_hard_regs), regno);
1200 }
1201 }
1202 }
1203}
1204
1205#endif
1206
1207/* Process insns of the basic block given by its LOOP_TREE_NODE to
1208 update allocno live ranges, allocno hard register conflicts,
1209 intersected calls, and register pressure info for allocnos for the
1210 basic block for and regions containing the basic block. */
1211static void
1212process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
1213{
1214 int i, freq;
1215 unsigned int j;
1216 basic_block bb;
1217 rtx_insn *insn;
1218 bitmap_iterator bi;
1219 bitmap reg_live_out;
1220 unsigned int px;
1221 bool set_p;
1222
1223 bb = loop_tree_node->bb;
1224 if (bb != NULLnullptr)
1225 {
1226 for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
1227 {
1228 curr_reg_pressure[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]] = 0;
1229 high_pressure_start_point[ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i]] = -1;
1230 }
1231 curr_bb_node = loop_tree_node;
1232 reg_live_out = df_get_live_out (bb);
1233 sparseset_clear (objects_live);
1234 REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out)do { CLEAR_HARD_REG_SET (hard_regs_live); reg_set_to_hard_reg_set
(&hard_regs_live, reg_live_out); } while (0)
;
1235 hard_regs_live &= ~(eliminable_regset | ira_no_alloc_regs(this_target_ira->x_ira_no_alloc_regs));
1236 for (i = 0; i < FIRST_PSEUDO_REGISTER76; i++)
1237 if (TEST_HARD_REG_BIT (hard_regs_live, i))
1238 {
1239 enum reg_class aclass, pclass, cl;
1240
1241 aclass = ira_allocno_class_translate(this_target_ira->x_ira_allocno_class_translate)[REGNO_REG_CLASS (i)(regclass_map[(i)])];
1242 pclass = ira_pressure_class_translate(this_target_ira->x_ira_pressure_class_translate)[aclass];
1243 for (j = 0;
1244 (cl = ira_reg_class_super_classes(this_target_ira_int->x_ira_reg_class_super_classes)[pclass][j])
1245 != LIM_REG_CLASSES;
1246 j++)
1247 {
1248 if (! ira_reg_pressure_class_p(this_target_ira_int->x_ira_reg_pressure_class_p)[cl])
1249 continue;
1250 curr_reg_pressure[cl]++;
1251 if (curr_bb_node->reg_pressure[cl] < curr_reg_pressure[cl])
1252 curr_bb_node->reg_pressure[cl] = curr_reg_pressure[cl];
1253 ira_assert (curr_reg_pressure[cl]((void)(!(curr_reg_pressure[cl] <= (this_target_ira->x_ira_class_hard_regs_num
)[cl]) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 1254, __FUNCTION__), 0 : 0))
1254 <= ira_class_hard_regs_num[cl])((void)(!(curr_reg_pressure[cl] <= (this_target_ira->x_ira_class_hard_regs_num
)[cl]) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 1254, __FUNCTION__), 0 : 0))
;
1255 }
1256 }
1257 EXECUTE_IF_SET_IN_BITMAP (reg_live_out, FIRST_PSEUDO_REGISTER, j, bi)for (bmp_iter_set_init (&(bi), (reg_live_out), (76), &
(j)); bmp_iter_set (&(bi), &(j)); bmp_iter_next (&
(bi), &(j)))
1258 mark_pseudo_regno_live (j);
1259
1260#ifdef EH_RETURN_DATA_REGNO
1261 process_out_of_region_eh_regs (bb);
1262#endif
1263
1264 freq = REG_FREQ_FROM_BB (bb)((optimize_function_for_size_p ((cfun + 0)) || !(cfun + 0)->
cfg->count_max.initialized_p ()) ? 1000 : ((bb)->count.
to_frequency ((cfun + 0)) * 1000 / 10000) ? ((bb)->count.to_frequency
((cfun + 0)) * 1000 / 10000) : 1)
;
1265 if (freq == 0)
1266 freq = 1;
1267
1268 /* Invalidate all allocno_saved_at_call entries. */
1269 last_call_num++;
1270
1271 /* Scan the code of this basic block, noting which allocnos and
1272 hard regs are born or die.
1273
1274 Note that this loop treats uninitialized values as live until
1275 the beginning of the block. For example, if an instruction
1276 uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1277 set, FOO will remain live until the beginning of the block.
1278 Likewise if FOO is not set at all. This is unnecessarily
1279 pessimistic, but it probably doesn't matter much in practice. */
1280 FOR_BB_INSNS_REVERSE (bb, insn)for ((insn) = (bb)->il.x.rtl->end_; (insn) && (
insn) != PREV_INSN ((bb)->il.x.head_); (insn) = PREV_INSN (
insn))
1281 {
1282 ira_allocno_t a;
1283 df_ref def, use;
1284 bool call_p;
1285
1286 if (!NONDEBUG_INSN_P (insn)((((enum rtx_code) (insn)->code) == INSN) || (((enum rtx_code
) (insn)->code) == JUMP_INSN) || (((enum rtx_code) (insn)->
code) == CALL_INSN))
)
1287 continue;
1288
1289 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULLnullptr)
1290 fprintf (ira_dump_file, " Insn %u(l%d): point = %d\n",
1291 INSN_UID (insn), loop_tree_node->parent->loop_num,
1292 curr_point);
1293
1294 call_p = CALL_P (insn)(((enum rtx_code) (insn)->code) == CALL_INSN);
1295 ignore_reg_for_conflicts = non_conflicting_reg_copy_p (insn);
1296
1297 /* Mark each defined value as live. We need to do this for
1298 unused values because they still conflict with quantities
1299 that are live at the time of the definition.
1300
1301 Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1302 references represent the effect of the called function
1303 on a call-clobbered register. Marking the register as
1304 live would stop us from allocating it to a call-crossing
1305 allocno. */
1306 FOR_EACH_INSN_DEF (def, insn)for (def = (((df->insns[(INSN_UID (insn))]))->defs); def
; def = ((def)->base.next_loc))
1307 if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)((((def)->base.flags) & (DF_REF_MAY_CLOBBER)) != 0))
1308 mark_ref_live (def);
1309
1310 /* If INSN has multiple outputs, then any value used in one
1311 of the outputs conflicts with the other outputs. Model this
1312 by making the used value live during the output phase.
1313
1314 It is unsafe to use !single_set here since it will ignore
1315 an unused output. Just because an output is unused does
1316 not mean the compiler can assume the side effect will not
1317 occur. Consider if ALLOCNO appears in the address of an
1318 output and we reload the output. If we allocate ALLOCNO
1319 to the same hard register as an unused output we could
1320 set the hard register before the output reload insn. */
1321 if (GET_CODE (PATTERN (insn))((enum rtx_code) (PATTERN (insn))->code) == PARALLEL && multiple_sets (insn))
1322 FOR_EACH_INSN_USE (use, insn)for (use = (((df->insns[(INSN_UID (insn))]))->uses); use
; use = ((use)->base.next_loc))
1323 {
1324 int i;
1325 rtx reg;
1326
1327 reg = DF_REF_REG (use)((use)->base.reg);
1328 for (i = XVECLEN (PATTERN (insn), 0)(((((PATTERN (insn))->u.fld[0]).rt_rtvec))->num_elem) - 1; i >= 0; i--)
1329 {
1330 rtx set;
1331
1332 set = XVECEXP (PATTERN (insn), 0, i)(((((PATTERN (insn))->u.fld[0]).rt_rtvec))->elem[i]);
1333 if (GET_CODE (set)((enum rtx_code) (set)->code) == SET
1334 && reg_overlap_mentioned_p (reg, SET_DEST (set)(((set)->u.fld[0]).rt_rtx)))
1335 {
1336 /* After the previous loop, this is a no-op if
1337 REG is contained within SET_DEST (SET). */
1338 mark_ref_live (use);
1339 break;
1340 }
1341 }
1342 }
1343
1344 preferred_alternatives = ira_setup_alts (insn);
1345 process_single_reg_class_operands (false, freq);
1346
1347 if (call_p)
1348 {
1349 /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1350 there, try to find a pseudo that is live across the call but
1351 can be cheaply reconstructed from the return value. */
1352 rtx cheap_reg = find_call_crossed_cheap_reg (insn);
1353 if (cheap_reg != NULL_RTX(rtx) 0)
1354 add_reg_note (insn, REG_RETURNED, cheap_reg);
1355
1356 last_call_num++;
1357 sparseset_clear (allocnos_processed);
1358 /* The current set of live allocnos are live across the call. */
1359 EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)for (sparseset_iter_init (objects_live); sparseset_iter_p (objects_live
) && (((i) = sparseset_iter_elm (objects_live)) || 1)
; sparseset_iter_next (objects_live))
1360 {
1361 ira_object_t obj = ira_object_id_map[i];
1362 a = OBJECT_ALLOCNO (obj)((obj)->allocno);
1363 int num = ALLOCNO_NUM (a)((a)->num);
1364 function_abi callee_abi = insn_callee_abi (insn);
1365
1366 /* Don't allocate allocnos that cross setjmps or any
1367 call, if this function receives a nonlocal
1368 goto. */
1369 if (cfun(cfun + 0)->has_nonlocal_label
1370 || (!targetm.setjmp_preserves_nonvolatile_regs_p ()
1371 && (find_reg_note (insn, REG_SETJMP, NULL_RTX(rtx) 0)
1372 != NULL_RTX(rtx) 0)))
1373 {
1374 SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj)((obj)->conflict_hard_regs));
1375 SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)((obj)->total_conflict_hard_regs));
1376 }
1377 if (can_throw_internal (insn))
1378 {
1379 OBJECT_CONFLICT_HARD_REGS (obj)((obj)->conflict_hard_regs)
1380 |= callee_abi.mode_clobbers (ALLOCNO_MODE (a)((a)->mode));
1381 OBJECT_TOTAL_CONFLICT_HARD_REGS (obj)((obj)->total_conflict_hard_regs)
1382 |= callee_abi.mode_clobbers (ALLOCNO_MODE (a)((a)->mode));
1383 }
1384
1385 if (sparseset_bit_p (allocnos_processed, num))
1386 continue;
1387 sparseset_set_bit (allocnos_processed, num);
1388
1389 if (allocno_saved_at_call[num] != last_call_num)
1390 /* Here we are mimicking caller-save.c behavior
1391 which does not save hard register at a call if
1392 it was saved on previous call in the same basic
1393 block and the hard register was not mentioned
1394 between the two calls. */
1395 ALLOCNO_CALL_FREQ (a)((a)->call_freq) += freq;
1396 /* Mark it as saved at the next call. */
1397 allocno_saved_at_call[num] = last_call_num + 1;
1398 ALLOCNO_CALLS_CROSSED_NUM (a)((a)->calls_crossed_num)++;
1399 ALLOCNO_CROSSED_CALLS_ABIS (a)((a)->crossed_calls_abis) |= 1 << callee_abi.id ();
1400 ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a)((a)->crossed_calls_clobbered_regs)
1401 |= callee_abi.full_and_partial_reg_clobbers ();
1402 if (cheap_reg != NULL_RTX(rtx) 0
1403 && ALLOCNO_REGNO (a)((a)->regno) == (int) REGNO (cheap_reg)(rhs_regno(cheap_reg)))
1404 ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)((a)->cheap_calls_crossed_num)++;
1405 }
1406 }
1407
1408 /* See which defined values die here. Note that we include
1409 the call insn in the lifetimes of these values, so we don't
1410 mistakenly consider, for e.g. an addressing mode with a
1411 side-effect like a post-increment fetching the address,
1412 that the use happens before the call, and the def to happen
1413 after the call: we believe both to happen before the actual
1414 call. (We don't handle return-values here.) */
1415 FOR_EACH_INSN_DEF (def, insn)for (def = (((df->insns[(INSN_UID (insn))]))->defs); def
; def = ((def)->base.next_loc))
1416 if (!call_p || !DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)((((def)->base.flags) & (DF_REF_MAY_CLOBBER)) != 0))
1417 mark_ref_dead (def);
1418
1419 make_early_clobber_and_input_conflicts ();
1420
1421 curr_point++;
1422
1423 /* Mark each used value as live. */
1424 FOR_EACH_INSN_USE (use, insn)for (use = (((df->insns[(INSN_UID (insn))]))->uses); use
; use = ((use)->base.next_loc))
1425 mark_ref_live (use);
1426
1427 process_single_reg_class_operands (true, freq);
1428
1429 set_p = mark_hard_reg_early_clobbers (insn, true);
1430
1431 if (set_p)
1432 {
1433 mark_hard_reg_early_clobbers (insn, false);
1434
1435 /* Mark each hard reg as live again. For example, a
1436 hard register can be in clobber and in an insn
1437 input. */
1438 FOR_EACH_INSN_USE (use, insn)for (use = (((df->insns[(INSN_UID (insn))]))->uses); use
; use = ((use)->base.next_loc))
1439 {
1440 rtx ureg = DF_REF_REG (use)((use)->base.reg);
1441
1442 if (GET_CODE (ureg)((enum rtx_code) (ureg)->code) == SUBREG)
1443 ureg = SUBREG_REG (ureg)(((ureg)->u.fld[0]).rt_rtx);
1444 if (! REG_P (ureg)(((enum rtx_code) (ureg)->code) == REG) || REGNO (ureg)(rhs_regno(ureg)) >= FIRST_PSEUDO_REGISTER76)
1445 continue;
1446
1447 mark_ref_live (use);
1448 }
1449 }
1450
1451 curr_point++;
1452 }
1453 ignore_reg_for_conflicts = NULL_RTX(rtx) 0;
1454
1455 if (bb_has_eh_pred (bb))
1456 for (j = 0; ; ++j)
1457 {
1458 unsigned int regno = EH_RETURN_DATA_REGNO (j)((j) <= 1 ? (j) : (~(unsigned int) 0));
1459 if (regno == INVALID_REGNUM(~(unsigned int) 0))
1460 break;
1461 make_hard_regno_live (regno);
1462 }
1463
1464 /* Allocnos can't go in stack regs at the start of a basic block
1465 that is reached by an abnormal edge. Likewise for registers
1466 that are at least partly call clobbered, because caller-save,
1467 fixup_abnormal_edges and possibly the table driven EH machinery
1468 are not quite ready to handle such allocnos live across such
1469 edges. */
1470 if (bb_has_abnormal_pred (bb))
1471 {
1472#ifdef STACK_REGS
1473 EXECUTE_IF_SET_IN_SPARSESET (objects_live, px)for (sparseset_iter_init (objects_live); sparseset_iter_p (objects_live
) && (((px) = sparseset_iter_elm (objects_live)) || 1
); sparseset_iter_next (objects_live))
1474 {
1475 ira_allocno_t a = OBJECT_ALLOCNO (ira_object_id_map[px])((ira_object_id_map[px])->allocno);
1476
1477 ALLOCNO_NO_STACK_REG_P (a)((a)->no_stack_reg_p) = true;
1478 ALLOCNO_TOTAL_NO_STACK_REG_P (a)((a)->total_no_stack_reg_p) = true;
1479 }
1480 for (px = FIRST_STACK_REG8; px <= LAST_STACK_REG15; px++)
1481 make_hard_regno_live (px);
1482#endif
1483 /* No need to record conflicts for call clobbered regs if we
1484 have nonlocal labels around, as we don't ever try to
1485 allocate such regs in this case. */
1486 if (!cfun(cfun + 0)->has_nonlocal_label
1487 && has_abnormal_call_or_eh_pred_edge_p (bb))
1488 for (px = 0; px < FIRST_PSEUDO_REGISTER76; px++)
1489 if (eh_edge_abi(this_target_function_abi_info->x_function_abis[0]).clobbers_at_least_part_of_reg_p (px)
1490#ifdef REAL_PIC_OFFSET_TABLE_REGNUM(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
0) ? 43 : 3)
1491 /* We should create a conflict of PIC pseudo with
1492 PIC hard reg as PIC hard reg can have a wrong
1493 value after jump described by the abnormal edge.
1494 In this case we cannot allocate PIC hard reg to
1495 PIC pseudo as PIC pseudo will also have a wrong
1496 value. This code is not critical as LRA can fix
1497 it but it is better to have the right allocation
1498 earlier. */
1499 || (px == REAL_PIC_OFFSET_TABLE_REGNUM(((global_options.x_ix86_isa_flags & (1UL << 1)) !=
0) ? 43 : 3)
1500 && pic_offset_table_rtx(this_target_rtl->x_pic_offset_table_rtx) != NULL_RTX(rtx) 0
1501 && REGNO (pic_offset_table_rtx)(rhs_regno((this_target_rtl->x_pic_offset_table_rtx))) >= FIRST_PSEUDO_REGISTER76)
1502#endif
1503 )
1504 make_hard_regno_live (px);
1505 }
1506
1507 EXECUTE_IF_SET_IN_SPARSESET (objects_live, i)for (sparseset_iter_init (objects_live); sparseset_iter_p (objects_live
) && (((i) = sparseset_iter_elm (objects_live)) || 1)
; sparseset_iter_next (objects_live))
1508 make_object_dead (ira_object_id_map[i]);
1509
1510 curr_point++;
1511
1512 }
1513 /* Propagate register pressure to upper loop tree nodes. */
1514 if (loop_tree_node != ira_loop_tree_root)
1515 for (i = 0; i < ira_pressure_classes_num(this_target_ira->x_ira_pressure_classes_num); i++)
1516 {
1517 enum reg_class pclass;
1518
1519 pclass = ira_pressure_classes(this_target_ira->x_ira_pressure_classes)[i];
1520 if (loop_tree_node->reg_pressure[pclass]
1521 > loop_tree_node->parent->reg_pressure[pclass])
1522 loop_tree_node->parent->reg_pressure[pclass]
1523 = loop_tree_node->reg_pressure[pclass];
1524 }
1525}
1526
1527/* Create and set up IRA_START_POINT_RANGES and
1528 IRA_FINISH_POINT_RANGES. */
1529static void
1530create_start_finish_chains (void)
1531{
1532 ira_object_t obj;
1533 ira_object_iterator oi;
1534 live_range_t r;
1535
1536 ira_start_point_ranges
1537 = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1538 memset (ira_start_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1539 ira_finish_point_ranges
1540 = (live_range_t *) ira_allocate (ira_max_point * sizeof (live_range_t));
1541 memset (ira_finish_point_ranges, 0, ira_max_point * sizeof (live_range_t));
1542 FOR_EACH_OBJECT (obj, oi)for (ira_object_iter_init (&(oi)); ira_object_iter_cond (
&(oi), &(obj));)
1543 for (r = OBJECT_LIVE_RANGES (obj)((obj)->live_ranges); r != NULLnullptr; r = r->next)
1544 {
1545 r->start_next = ira_start_point_ranges[r->start];
1546 ira_start_point_ranges[r->start] = r;
1547 r->finish_next = ira_finish_point_ranges[r->finish];
1548 ira_finish_point_ranges[r->finish] = r;
1549 }
1550}
1551
1552/* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1553 new live ranges and program points were added as a result if new
1554 insn generation. */
1555void
1556ira_rebuild_start_finish_chains (void)
1557{
1558 ira_free (ira_finish_point_ranges);
1559 ira_free (ira_start_point_ranges);
1560 create_start_finish_chains ();
1561}
1562
1563/* Compress allocno live ranges by removing program points where
1564 nothing happens. */
1565static void
1566remove_some_program_points_and_update_live_ranges (void)
1567{
1568 unsigned i;
1569 int n;
1570 int *map;
1571 ira_object_t obj;
1572 ira_object_iterator oi;
1573 live_range_t r, prev_r, next_r;
1574 sbitmap_iterator sbi;
1575 bool born_p, dead_p, prev_born_p, prev_dead_p;
1576
1577 auto_sbitmap born (ira_max_point);
1578 auto_sbitmap dead (ira_max_point);
1579 bitmap_clear (born);
1580 bitmap_clear (dead);
1581 FOR_EACH_OBJECT (obj, oi)for (ira_object_iter_init (&(oi)); ira_object_iter_cond (
&(oi), &(obj));)
1582 for (r = OBJECT_LIVE_RANGES (obj)((obj)->live_ranges); r != NULLnullptr; r = r->next)
1583 {
1584 ira_assert (r->start <= r->finish)((void)(!(r->start <= r->finish) ? fancy_abort ("/home/marxin/BIG/buildbot/buildworker/marxinbox-gcc-clang-static-analyzer/build/gcc/ira-lives.c"
, 1584, __FUNCTION__), 0 : 0))
;
1585 bitmap_set_bit (born, r->start);
1586 bitmap_set_bit (dead, r->finish);
1587 }
1588
1589 auto_sbitmap born_or_dead (ira_max_point);
1590 bitmap_ior (born_or_dead, born, dead);
1591 map = (int *) ira_allocate (sizeof (int) * ira_max_point);
1592 n = -1;
1593 prev_born_p = prev_dead_p = false;
1594 EXECUTE_IF_SET_IN_BITMAP (born_or_dead, 0, i, sbi)for (bmp_iter_set_init (&(sbi), (born_or_dead), (0), &
(i)); bmp_iter_set (&(sbi), &(i)); bmp_iter_next (&
(sbi), &(i)))
1595 {
1596 born_p = bitmap_bit_p (born, i);
1597 dead_p = bitmap_bit_p (dead, i);
1598 if ((prev_born_p && ! prev_dead_p && born_p && ! dead_p)
1599 || (prev_dead_p && ! prev_born_p && dead_p && ! born_p))
1600 map[i] = n;
1601 else
1602 map[i] = ++n;
1603 prev_born_p = born_p;
1604 prev_dead_p = dead_p;
1605 }
1606
1607 n++;
1608 if (internal_flag_ira_verbose > 1 && ira_dump_file != NULLnullptr)
1609 fprintf (ira_dump_file, "Compressing live ranges: from %d to %d - %d%%\n",
1610 ira_max_point, n, 100 * n / ira_max_point);
1611 ira_max_point = n;
1612
1613 FOR_EACH_OBJECT (obj, oi)for (ira_object_iter_init (&(oi)); ira_object_iter_cond (
&(oi), &(obj));)
1614 for (r = OBJECT_LIVE_RANGES (obj)((obj)->live_ranges), prev_r = NULLnullptr; r != NULLnullptr; r = next_r)
1615 {
1616 next_r = r->next;
1617 r->start = map[r->start];
1618 r->finish = map[r->finish];
1619 if (prev_r == NULLnullptr || prev_r->start > r->finish + 1)
1620 {
1621 prev_r = r;
1622 continue;
1623 }
1624 prev_r->start = r->start;
1625 prev_r->next = next_r;
1626 ira_finish_live_range (r);
1627 }
1628
1629 ira_free (map);
1630}
1631
1632/* Print live ranges R to file F. */
1633void
1634ira_print_live_range_list (FILE *f, live_range_t r)
1635{
1636 for (; r != NULLnullptr; r = r->next)
1637 fprintf (f, " [%d..%d]", r->start, r->finish);
1638 fprintf (f, "\n");
1639}
1640
1641DEBUG_FUNCTION__attribute__ ((__used__)) void
1642debug (live_range &ref)
1643{
1644 ira_print_live_range_list (stderrstderr, &ref);
1645}
1646
1647DEBUG_FUNCTION__attribute__ ((__used__)) void
1648debug (live_range *ptr)
1649{
1650 if (ptr)
1651 debug (*ptr);
1652 else
1653 fprintf (stderrstderr, "<nil>\n");
1654}
1655
1656/* Print live ranges R to stderr. */
1657void
1658ira_debug_live_range_list (live_range_t r)
1659{
1660 ira_print_live_range_list (stderrstderr, r);
1661}
1662
1663/* Print live ranges of object OBJ to file F. */
1664static void
1665print_object_live_ranges (FILE *f, ira_object_t obj)
1666{
1667 ira_print_live_range_list (f, OBJECT_LIVE_RANGES (obj)((obj)->live_ranges));
1668}
1669
1670/* Print live ranges of allocno A to file F. */
1671static void
1672print_allocno_live_ranges (FILE *f, ira_allocno_t a)
1673{
1674 int n = ALLOCNO_NUM_OBJECTS (a)((a)->num_objects);
1675 int i;
1676
1677 for (i = 0; i < n; i++)
1678 {
1679 fprintf (f, " a%d(r%d", ALLOCNO_NUM (a)((a)->num), ALLOCNO_REGNO (a)((a)->regno));
1680 if (n > 1)
1681 fprintf (f, " [%d]", i);
1682 fprintf (f, "):");
1683 print_object_live_ranges (f, ALLOCNO_OBJECT (a, i)((a)->objects[i]));
1684 }
1685}
1686
1687/* Print live ranges of allocno A to stderr. */
1688void
1689ira_debug_allocno_live_ranges (ira_allocno_t a)
1690{
1691 print_allocno_live_ranges (stderrstderr, a);
1692}
1693
1694/* Print live ranges of all allocnos to file F. */
1695static void
1696print_live_ranges (FILE *f)
1697{
1698 ira_allocno_t a;
1699 ira_allocno_iterator ai;
1700
1701 FOR_EACH_ALLOCNO (a, ai)for (ira_allocno_iter_init (&(ai)); ira_allocno_iter_cond
(&(ai), &(a));)
1702 print_allocno_live_ranges (f, a);
1703}
1704
1705/* Print live ranges of all allocnos to stderr. */
1706void
1707ira_debug_live_ranges (void)
1708{
1709 print_live_ranges (stderrstderr);
1710}
1711
1712/* The main entry function creates live ranges, set up
1713 CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1714 calculate register pressure info. */
1715void
1716ira_create_allocno_live_ranges (void)
1717{
1718 objects_live = sparseset_alloc (ira_objects_num);
1719 allocnos_processed = sparseset_alloc (ira_allocnos_num);
1720 curr_point = 0;
1721 last_call_num = 0;
1722 allocno_saved_at_call
1723 = (int *) ira_allocate (ira_allocnos_num * sizeof (int));
1724 memset (allocno_saved_at_call, 0, ira_allocnos_num * sizeof (int));
1725 ira_traverse_loop_tree (true, ira_loop_tree_root, NULLnullptr,
1726 process_bb_node_lives);
1727 ira_max_point = curr_point;
1728 create_start_finish_chains ();
1729 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULLnullptr)
1730 print_live_ranges (ira_dump_file);
1731 /* Clean up. */
1732 ira_free (allocno_saved_at_call);
1733 sparseset_free (objects_live)free(objects_live);
1734 sparseset_free (allocnos_processed)free(allocnos_processed);
1735}
1736
1737/* Compress allocno live ranges. */
1738void
1739ira_compress_allocno_live_ranges (void)
1740{
1741 remove_some_program_points_and_update_live_ranges ();
1742 ira_rebuild_start_finish_chains ();
1743 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULLnullptr)
1744 {
1745 fprintf (ira_dump_file, "Ranges after the compression:\n");
1746 print_live_ranges (ira_dump_file);
1747 }
1748}
1749
1750/* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1751void
1752ira_finish_allocno_live_ranges (void)
1753{
1754 ira_free (ira_finish_point_ranges);
1755 ira_free (ira_start_point_ranges);
1756}