LCOV - code coverage report
Current view: top level - gcc/config/i386 - constraints.md (source / functions) Hit Total Coverage
Test: gcc.info Lines: 82 84 97.6 %
Date: 2020-03-28 11:57:23 Functions: 22 22 100.0 %
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           Branch data     Line data    Source code
       1                 :            : ;; Constraint definitions for IA-32 and x86-64.
       2                 :            : ;; Copyright (C) 2006-2020 Free Software Foundation, Inc.
       3                 :            : ;;
       4                 :            : ;; This file is part of GCC.
       5                 :            : ;;
       6                 :            : ;; GCC is free software; you can redistribute it and/or modify
       7                 :            : ;; it under the terms of the GNU General Public License as published by
       8                 :            : ;; the Free Software Foundation; either version 3, or (at your option)
       9                 :            : ;; any later version.
      10                 :            : ;;
      11                 :            : ;; GCC is distributed in the hope that it will be useful,
      12                 :            : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
      13                 :            : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
      14                 :            : ;; GNU General Public License for more details.
      15                 :            : ;;
      16                 :            : ;; You should have received a copy of the GNU General Public License
      17                 :            : ;; along with GCC; see the file COPYING3.  If not see
      18                 :            : ;; <http://www.gnu.org/licenses/>.
      19                 :            : 
      20                 :            : ;;; Unused letters:
      21                 :            : ;;;           H
      22                 :            : ;;;           h j               z
      23                 :            : 
      24                 :            : ;; Integer register constraints.
      25                 :            : ;; It is not necessary to define 'r' here.
      26                 :            : (define_register_constraint "R" "LEGACY_REGS"
      27                 :            :  "Legacy register---the eight integer registers available on all
      28                 :            :   i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
      29                 :            :   @code{si}, @code{di}, @code{bp}, @code{sp}).")
      30                 :            : 
      31                 :            : (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
      32                 :            :  "Any register accessible as @code{@var{r}l}.  In 32-bit mode, @code{a},
      33                 :            :   @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.")
      34                 :            : 
      35                 :            : (define_register_constraint "Q" "Q_REGS"
      36                 :            :  "Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
      37                 :            :   @code{c}, and @code{d}.")
      38                 :            : 
      39                 :            : (define_register_constraint "l" "INDEX_REGS"
      40                 :            :  "@internal Any register that can be used as the index in a base+index
      41                 :            :   memory access: that is, any general register except the stack pointer.")
      42                 :            : 
      43                 :            : (define_register_constraint "a" "AREG"
      44                 :            :  "The @code{a} register.")
      45                 :            : 
      46                 :            : (define_register_constraint "b" "BREG"
      47                 :            :  "The @code{b} register.")
      48                 :            : 
      49                 :            : (define_register_constraint "c" "CREG"
      50                 :            :  "The @code{c} register.")
      51                 :            : 
      52                 :            : (define_register_constraint "d" "DREG"
      53                 :            :  "The @code{d} register.")
      54                 :            : 
      55                 :            : (define_register_constraint "S" "SIREG"
      56                 :            :  "The @code{si} register.")
      57                 :            : 
      58                 :            : (define_register_constraint "D" "DIREG"
      59                 :            :  "The @code{di} register.")
      60                 :            : 
      61                 :            : (define_register_constraint "A" "AD_REGS"
      62                 :            :  "The @code{a} and @code{d} registers, as a pair (for instructions
      63                 :            :   that return half the result in one and half in the other).")
      64                 :            : 
      65                 :            : (define_register_constraint "U" "CLOBBERED_REGS"
      66                 :            :  "The call-clobbered integer registers.")
      67                 :            : 
      68                 :            : ;; Floating-point register constraints.
      69                 :            : (define_register_constraint "f"
      70                 :            :  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS"
      71                 :            :  "Any 80387 floating-point (stack) register.")
      72                 :            : 
      73                 :            : (define_register_constraint "t"
      74                 :            :  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS"
      75                 :            :  "Top of 80387 floating-point stack (@code{%st(0)}).")
      76                 :            : 
      77                 :            : (define_register_constraint "u"
      78                 :            :  "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
      79                 :            :  "Second from top of 80387 floating-point stack (@code{%st(1)}).")
      80                 :            : 
      81                 :            : (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_REGS : NO_REGS"
      82                 :            : "@internal Any mask register that can be used as predicate, i.e. k1-k7.")
      83                 :            : 
      84                 :            : (define_register_constraint "k" "TARGET_AVX512F ? ALL_MASK_REGS : NO_REGS"
      85                 :            : "@internal Any mask register.")
      86                 :            : 
      87                 :            : ;; Vector registers (also used for plain floating point nowadays).
      88                 :            : (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
      89                 :            :  "Any MMX register.")
      90                 :            : 
      91                 :            : (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
      92                 :            :  "Any SSE register.")
      93                 :            : 
      94                 :            : (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
      95                 :            :  "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
      96                 :            : 
      97                 :            : ;; We use the Y prefix to denote any number of conditional register sets:
      98                 :            : ;;  z   First SSE register.
      99                 :            : ;;  d   any EVEX encodable SSE register for AVX512DQ target or
     100                 :            : ;;      any SSE register for SSE4_1 target.
     101                 :            : ;;  p   Integer register when TARGET_PARTIAL_REG_STALL is disabled
     102                 :            : ;;  a   Integer register when zero extensions with AND are disabled
     103                 :            : ;;  b   Any register that can be used as the GOT base when calling
     104                 :            : ;;      ___tls_get_addr: that is, any general register except EAX
     105                 :            : ;;      and ESP, for -fno-plt if linker supports it.  Otherwise,
     106                 :            : ;;      EBX.
     107                 :            : ;;  f   x87 register when 80387 floating point arithmetic is enabled
     108                 :            : ;;  r   SSE regs not requiring REX prefix when prefixes avoidance is enabled
     109                 :            : ;;      and all SSE regs otherwise
     110                 :            : ;;  v   any EVEX encodable SSE register for AVX512VL target,
     111                 :            : ;;      otherwise any SSE register
     112                 :            : ;;  w   any EVEX encodable SSE register for AVX512BW with TARGET_AVX512VL
     113                 :            : ;;      target.
     114                 :            : 
     115                 :            : (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
     116                 :            :  "First SSE register (@code{%xmm0}).")
     117                 :            : 
     118                 :            : (define_register_constraint "Yd"
     119                 :            :  "TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
     120                 :            :  "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.")
     121                 :            : 
     122                 :            : (define_register_constraint "Yp"
     123                 :            :  "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
     124                 :            :  "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.")
     125                 :            : 
     126                 :            : (define_register_constraint "Ya"
     127                 :            :  "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)
     128                 :            :   ? NO_REGS : GENERAL_REGS"
     129                 :            :  "@internal Any integer register when zero extensions with AND are disabled.")
     130                 :            : 
     131                 :            : (define_register_constraint "Yb"
     132                 :            :  "(!flag_plt && HAVE_AS_IX86_TLS_GET_ADDR_GOT) ? TLS_GOTBASE_REGS : BREG"
     133                 :            :  "@internal Any register that can be used as the GOT base when calling
     134                 :            :   ___tls_get_addr: that is, any general register except @code{a} and
     135                 :            :   @code{sp} registers, for -fno-plt if linker supports it.  Otherwise,
     136                 :            :   @code{b} register.")
     137                 :            : 
     138                 :            : (define_register_constraint "Yf"
     139                 :            :  "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS"
     140                 :            :  "@internal Any x87 register when 80387 FP arithmetic is enabled.")
     141                 :            : 
     142                 :            : (define_register_constraint "Yr"
     143                 :            :  "TARGET_SSE ? (TARGET_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS"
     144                 :            :  "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.")
     145                 :            : 
     146                 :            : (define_register_constraint "Yv"
     147                 :            :  "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
     148                 :            :  "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.")
     149                 :            : 
     150                 :            : (define_register_constraint "Yw"
     151                 :            :  "TARGET_AVX512BW && TARGET_AVX512VL ? ALL_SSE_REGS : NO_REGS"
     152                 :            :  "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW with TARGET_AVX512VL target.")
     153                 :            : 
     154                 :            : ;; We use the B prefix to denote any number of internal operands:
     155                 :            : ;;  f  FLAGS_REG
     156                 :            : ;;  g  GOT memory operand.
     157                 :            : ;;  m  Vector memory operand
     158                 :            : ;;  c  Constant memory operand
     159                 :            : ;;  n  Memory operand without REX prefix
     160                 :            : ;;  s  Sibcall memory operand, not valid for TARGET_X32
     161                 :            : ;;  w  Call memory operand, not valid for TARGET_X32
     162                 :            : ;;  z  Constant call address operand.
     163                 :            : ;;  C  SSE constant operand.
     164                 :            : 
     165                 :            : (define_constraint "Bf"
     166                 :            :   "@internal Flags register operand."
     167                 :            :   (match_operand 0 "flags_reg_operand"))
     168                 :            : 
     169                 :            : (define_constraint "Bg"
     170                 :            :   "@internal GOT memory operand."
     171                 :            :   (match_operand 0 "GOT_memory_operand"))
     172                 :            : 
     173                 :            : (define_special_memory_constraint "Bm"
     174                 :            :   "@internal Vector memory operand."
     175                 :            :   (match_operand 0 "vector_memory_operand"))
     176                 :            : 
     177                 :            : (define_special_memory_constraint "Bc"
     178                 :            :   "@internal Constant memory operand."
     179                 :            :   (and (match_operand 0 "memory_operand")
     180                 :       4944 :        (match_test "constant_address_p (XEXP (op, 0))")))
     181                 :            : 
     182                 :            : (define_special_memory_constraint "Bn"
     183                 :        592 :   "@internal Memory operand without REX prefix."
     184                 :            :   (match_operand 0 "norex_memory_operand"))
     185                 :        592 : 
     186                 :        592 : (define_constraint "Bs"
     187                 :            :   "@internal Sibcall memory operand."
     188                 :    2596020 :   (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
     189                 :     865107 :             (not (match_test "TARGET_X32"))
     190                 :            :             (match_operand 0 "sibcall_memory_operand"))
     191                 :     856281 :        (and (match_test "TARGET_X32 && Pmode == DImode")
     192                 :     865483 :             (match_operand 0 "GOT_memory_operand"))))
     193                 :            : 
     194                 :   32742000 : (define_constraint "Bw"
     195                 :            :   "@internal Call memory operand."
     196                 :   98225900 :   (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
     197                 :   32742000 :             (not (match_test "TARGET_X32"))
     198                 :            :             (match_operand 0 "memory_operand"))
     199                 :   32176200 :        (and (match_test "TARGET_X32 && Pmode == DImode")
     200                 :            :             (match_operand 0 "GOT_memory_operand"))))
     201                 :            : 
     202                 :   33447100 : (define_constraint "Bz"
     203                 :            :   "@internal Constant call address operand."
     204                 :   33447100 :   (match_operand 0 "constant_call_address_operand"))
     205                 :   33447100 : 
     206                 :            : (define_constraint "BC"
     207                 :            :   "@internal SSE constant -1 operand."
     208                 :  107340000 :   (and (match_test "TARGET_SSE")
     209                 :   53669700 :        (ior (match_test "op == constm1_rtx")
     210                 :   53670000 :             (match_operand 0 "vector_all_ones_operand"))))
     211                 :   53670000 : 
     212                 :    1814910 : ;; Integer constant constraints.
     213                 :            : (define_constraint "I"
     214                 :    1814910 :   "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
     215                 :    1814910 :   (and (match_code "const_int")
     216                 :    2330220 :        (match_test "IN_RANGE (ival, 0, 31)")))
     217                 :    1814910 : 
     218                 :    1308930 : (define_constraint "J"
     219                 :    4663390 :   "Integer constant in the range 0 @dots{} 63, for 64-bit shifts."
     220                 :            :   (and (match_code "const_int")
     221                 :    1308930 :        (match_test "IN_RANGE (ival, 0, 63)")))
     222                 :    3354460 : 
     223                 :    3185610 : (define_constraint "K"
     224                 :  142285755 :   "Signed 8-bit integer constant."
     225                 :            :   (and (match_code "const_int")
     226                 :  277200476 :        (match_test "IN_RANGE (ival, -128, 127)")))
     227                 :  140319611 : 
     228                 :  138436352 : (define_constraint "L"
     229                 :  140435158 :   "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF}
     230                 :            :    for AND as a zero-extending move."
     231                 :      72318 :   (and (match_code "const_int")
     232                 :      72318 :        (match_test "ival == 0xff || ival == 0xffff
     233                 :     708035 :                     || ival == (HOST_WIDE_INT) 0xffffffff")))
     234                 :      72318 : 
     235                 :     968143 : (define_constraint "M"
     236                 :    1098720 :   "0, 1, 2, or 3 (shifts for the @code{lea} instruction)."
     237                 :            :   (and (match_code "const_int")
     238                 :     968143 :        (match_test "IN_RANGE (ival, 0, 3)")))
     239                 :     130582 : 
     240                 :     129941 : (define_constraint "N"
     241                 :     130582 :   "Unsigned 8-bit integer constant (for @code{in} and @code{out}
     242                 :            :    instructions)."
     243                 :     311199 :   (and (match_code "const_int")
     244                 :     416220 :        (match_test "IN_RANGE (ival, 0, 255)")))
     245                 :     303865 : 
     246                 :     311199 : (define_constraint "O"
     247                 :      58042 :   "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts."
     248                 :            :   (and (match_code "const_int")
     249                 :      31859 :        (match_test "IN_RANGE (ival, 0, 127)")))
     250                 :      26183 : 
     251                 :      25002 : ;; Floating-point constant constraints.
     252                 :      26183 : ;; We allow constants even if TARGET_80387 isn't set, because the
     253                 :            : ;; stack register converter may need to load 0.0 into the function
     254                 :   30499500 : ;; value register (top of stack).
     255                 :            : (define_constraint "G"
     256                 :            :   "Standard 80387 floating point constant."
     257                 :            :   (and (match_code "const_double")
     258                 :     895629 :        (match_test "standard_80387_constant_p (op) > 0")))
     259                 :            : 
     260                 :            : ;; This can theoretically be any mode's CONST0_RTX.
     261                 :  253546000 : (define_constraint "C"
     262                 :            :   "Constant zero operand."
     263                 :  249272000 :   (ior (match_test "op == const0_rtx")
     264                 :  253546000 :        (match_operand 0 "const0_operand")))
     265                 :            : 
     266                 :  485166000 : ;; Constant-or-symbol-reference constraints.
     267                 :            : 
     268                 :  485166000 : (define_constraint "e"
     269                 :  485166000 :   "32-bit signed integer constant, or a symbolic reference known
     270                 :            :    to fit that range (for immediate operands in sign-extending x86-64
     271                 :            :    instructions)."
     272                 :     219201 :   (match_operand 0 "x86_64_immediate_operand"))
     273                 :            : 
     274                 :     219201 : ;; We use W prefix to denote any number of
     275                 :     219201 : ;; constant-or-symbol-reference constraints
     276                 :            : 
     277                 :            : (define_constraint "We"
     278                 :            :   "32-bit signed integer constant, or a symbolic reference known
     279                 :            :    to fit that range (for sign-extending conversion operations that
     280                 :            :    require non-VOIDmode immediate operands)."
     281                 :            :   (and (match_operand 0 "x86_64_immediate_operand")
     282                 :          0 :        (match_test "GET_MODE (op) != VOIDmode")))
     283                 :            : 
     284                 :            : (define_constraint "Wz"
     285                 :     800841 :   "32-bit unsigned integer constant, or a symbolic reference known
     286                 :            :    to fit that range (for zero-extending conversion operations that
     287                 :     800841 :    require non-VOIDmode immediate operands)."
     288                 :     800841 :   (and (match_operand 0 "x86_64_zext_immediate_operand")
     289                 :          0 :        (match_test "GET_MODE (op) != VOIDmode")))
     290                 :            : 
     291                 :            : (define_constraint "Wd"
     292                 :     105837 :   "128-bit integer constant where both the high and low 64-bit word
     293                 :            :    of it satisfies the e constraint."
     294                 :     105837 :   (match_operand 0 "x86_64_hilo_int_operand"))
     295                 :     105837 : 
     296                 :            : (define_constraint "Wf"
     297                 :            :   "32-bit signed integer constant zero extended from word size
     298                 :       1054 :    to double word size."
     299                 :            :   (match_operand 0 "x86_64_dwzext_immediate_operand"))
     300                 :       1054 : 
     301                 :       1054 : (define_constraint "Z"
     302                 :            :   "32-bit unsigned integer constant, or a symbolic reference known
     303                 :            :    to fit that range (for immediate operands in zero-extending x86-64
     304                 :  224431721 :    instructions)."
     305                 :            :   (match_operand 0 "x86_64_zext_immediate_operand"))
     306                 :  224431721 : 
     307                 :  224431721 : ;; T prefix is used for different address constraints
     308                 :            : ;;   v - VSIB address
     309                 :            : ;;   s - address with no segment register
     310                 :      17242 : ;;   i - address with no index and no rip
     311                 :            : ;;   b - address with no base and no rip
     312                 :      17242 : 
     313                 :      17242 : (define_address_constraint "Tv"
     314                 :            :   "VSIB address operand"
     315                 :            :   (match_operand 0 "vsib_address_operand"))
     316                 :   21496700 : 
     317                 :            : (define_address_constraint "Ts"
     318                 :   21496700 :   "Address operand without segment register"
     319                 :   21496700 :   (match_operand 0 "address_no_seg_operand"))

Generated by: LCOV version 1.0

LCOV profile is generated on x86_64 machine using following configure options: configure --disable-bootstrap --enable-coverage=opt --enable-languages=c,c++,fortran,go,jit,lto --enable-host-shared. GCC test suite is run with the built compiler.