LCOV - code coverage report
Current view: top level - gcc/config/i386 - subst.md (source / functions) Hit Total Coverage
Test: gcc.info Lines: 129 130 99.2 %
Date: 2020-03-28 11:57:23 Functions: 1 1 100.0 %
Legend: Lines: hit not hit | Branches: + taken - not taken # not executed Branches: 0 0 -

           Branch data     Line data    Source code
       1                 :            : ;; GCC machine description for AVX512F instructions
       2                 :            : ;; Copyright (C) 2013-2020 Free Software Foundation, Inc.
       3                 :            : ;;
       4                 :            : ;; This file is part of GCC.
       5                 :            : ;;
       6                 :            : ;; GCC is free software; you can redistribute it and/or modify
       7                 :            : ;; it under the terms of the GNU General Public License as published by
       8                 :            : ;; the Free Software Foundation; either version 3, or (at your option)
       9                 :            : ;; any later version.
      10                 :            : ;;
      11                 :            : ;; GCC is distributed in the hope that it will be useful,
      12                 :            : ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
      13                 :            : ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
      14                 :            : ;; GNU General Public License for more details.
      15                 :            : ;;
      16                 :            : ;; You should have received a copy of the GNU General Public License
      17                 :            : ;; along with GCC; see the file COPYING3.  If not see
      18                 :            : ;; <http://www.gnu.org/licenses/>.
      19                 :            : 
      20                 :            : ;; Some iterators for extending subst as much as possible
      21                 :            : ;; All vectors (Use it for destination)
      22                 :            : (define_mode_iterator SUBST_V
      23                 :            :   [V64QI V32QI V16QI
      24                 :            :    V32HI V16HI V8HI
      25                 :            :    V16SI V8SI  V4SI
      26                 :            :    V8DI  V4DI  V2DI
      27                 :            :    V16SF V8SF  V4SF
      28                 :            :    V8DF  V4DF  V2DF])
      29                 :            : 
      30                 :            : (define_mode_iterator SUBST_S
      31                 :            :   [QI HI SI DI])
      32                 :            : 
      33                 :            : (define_mode_iterator SUBST_A
      34                 :            :   [V64QI V32QI V16QI
      35                 :            :    V32HI V16HI V8HI
      36                 :            :    V16SI V8SI  V4SI
      37                 :            :    V8DI  V4DI  V2DI
      38                 :            :    V16SF V8SF  V4SF
      39                 :            :    V8DF  V4DF  V2DF
      40                 :            :    QI HI SI DI SF DF])
      41                 :            : 
      42                 :            : (define_subst_attr "mask_name" "mask" "" "_mask")
      43                 :            : (define_subst_attr "mask_applied" "mask" "false" "true")
      44                 :            : (define_subst_attr "mask_operand2" "mask" "" "%{%3%}%N2")
      45                 :            : (define_subst_attr "mask_operand3" "mask" "" "%{%4%}%N3")
      46                 :            : (define_subst_attr "mask_operand3_1" "mask" "" "%%{%%4%%}%%N3") ;; for sprintf
      47                 :            : (define_subst_attr "mask_operand4" "mask" "" "%{%5%}%N4")
      48                 :            : (define_subst_attr "mask_operand6" "mask" "" "%{%7%}%N6")
      49                 :            : (define_subst_attr "mask_operand7" "mask" "" "%{%8%}%N7")
      50                 :            : (define_subst_attr "mask_operand10" "mask" "" "%{%11%}%N10")
      51                 :            : (define_subst_attr "mask_operand11" "mask" "" "%{%12%}%N11")
      52                 :            : (define_subst_attr "mask_operand18" "mask" "" "%{%19%}%N18")
      53                 :            : (define_subst_attr "mask_operand19" "mask" "" "%{%20%}%N19")
      54                 :            : (define_subst_attr "mask_codefor" "mask" "*" "")
      55                 :            : (define_subst_attr "mask_operand_arg34" "mask" "" ", operands[3], operands[4]")
      56                 :            : (define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
      57                 :            : (define_subst_attr "mask_avx512vl_condition" "mask" "1" "TARGET_AVX512VL")
      58                 :            : (define_subst_attr "mask_avx512bw_condition" "mask" "1" "TARGET_AVX512BW")
      59                 :            : (define_subst_attr "mask_avx512dq_condition" "mask" "1" "TARGET_AVX512DQ")
      60                 :            : (define_subst_attr "store_mask_constraint" "mask" "vm" "v")
      61                 :            : (define_subst_attr "store_mask_predicate" "mask" "nonimmediate_operand" "register_operand")
      62                 :            : (define_subst_attr "mask_prefix" "mask" "vex" "evex")
      63                 :            : (define_subst_attr "mask_prefix2" "mask" "maybe_vex" "evex")
      64                 :            : (define_subst_attr "mask_prefix3" "mask" "orig,vex" "evex,evex")
      65                 :            : (define_subst_attr "mask_prefix4" "mask" "orig,orig,vex" "evex,evex,evex")
      66                 :            : (define_subst_attr "mask_expand_op3" "mask" "3" "5")
      67                 :            : 
      68                 :            : (define_subst "mask"
      69                 :            :   [(set (match_operand:SUBST_V 0)
      70                 :            :         (match_operand:SUBST_V 1))]
      71                 :      47029 :   "TARGET_AVX512F"
      72                 :        826 :   [(set (match_dup 0)
      73                 :       1034 :         (vec_merge:SUBST_V
      74                 :       1034 :           (match_dup 1)
      75                 :       2067 :           (match_operand:SUBST_V 2 "nonimm_or_0_operand" "0C")
      76                 :       9619 :           (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))])
      77                 :       5292 : 
      78                 :       1565 : (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask")
      79                 :        615 : (define_subst_attr "mask_scalar_merge_operand3" "mask_scalar_merge" "" "%{%3%}")
      80                 :       2828 : (define_subst_attr "mask_scalar_merge_operand4" "mask_scalar_merge" "" "%{%4%}")
      81                 :       1547 : 
      82                 :        257 : (define_subst "mask_scalar_merge"
      83                 :        695 :   [(set (match_operand:SUBST_S 0)
      84                 :       2296 :         (match_operand:SUBST_S 1))]
      85                 :       5097 :   "TARGET_AVX512F"
      86                 :       1221 :   [(set (match_dup 0)
      87                 :        608 :         (and:SUBST_S
      88                 :       1206 :           (match_dup 1)
      89                 :        492 :           (match_operand:SUBST_S 3 "register_operand" "Yk")))])
      90                 :        969 : 
      91                 :        536 : (define_subst_attr "sd_maskz_name" "sd" "" "_maskz_1")
      92                 :        405 : (define_subst_attr "sd_mask_op4" "sd" "" "%{%5%}%N4")
      93                 :        291 : (define_subst_attr "sd_mask_op5" "sd" "" "%{%6%}%N5")
      94                 :      22329 : (define_subst_attr "sd_mask_codefor" "sd" "*" "")
      95                 :        156 : (define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)")
      96                 :      18834 : 
      97                 :       1577 : (define_subst "sd"
      98                 :        460 :  [(set (match_operand:SUBST_V 0)
      99                 :        156 :        (match_operand:SUBST_V 1))]
     100                 :        611 :  ""
     101                 :        677 :  [(set (match_dup 0)
     102                 :        135 :        (vec_merge:SUBST_V
     103                 :        135 :          (match_dup 1)
     104                 :        716 :          (match_operand:SUBST_V 2 "const0_operand" "C")
     105                 :        562 :          (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))
     106                 :        135 : ])
     107                 :        437 : 
     108                 :        437 : (define_subst_attr "round_name" "round" "" "_round")
     109                 :        566 : (define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4")
     110                 :        302 : (define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5")
     111                 :        302 : (define_subst_attr "round_mask_operand4" "mask" "%R4" "%R6")
     112                 :        302 : (define_subst_attr "round_sd_mask_operand4" "sd" "%R4" "%R6")
     113                 :        302 : (define_subst_attr "round_op2" "round" "" "%R2")
     114                 :        302 : (define_subst_attr "round_op3" "round" "" "%R3")
     115                 :        302 : (define_subst_attr "round_op4" "round" "" "%R4")
     116                 :            : (define_subst_attr "round_op5" "round" "" "%R5")
     117                 :        302 : (define_subst_attr "round_op6" "round" "" "%R6")
     118                 :            : (define_subst_attr "round_mask_op2" "round" "" "<round_mask_operand2>")
     119                 :        136 : (define_subst_attr "round_mask_op3" "round" "" "<round_mask_operand3>")
     120                 :        136 : (define_subst_attr "round_mask_op4" "round" "" "<round_mask_operand4>")
     121                 :        136 : (define_subst_attr "round_sd_mask_op4" "round" "" "<round_sd_mask_operand4>")
     122                 :            : (define_subst_attr "round_constraint" "round" "vm" "v")
     123                 :            : (define_subst_attr "round_constraint2" "round" "m" "v")
     124                 :            : (define_subst_attr "round_constraint3" "round" "rm" "r")
     125                 :            : (define_subst_attr "round_nimm_predicate" "round" "vector_operand" "register_operand")
     126                 :            : (define_subst_attr "round_nimm_scalar_predicate" "round" "nonimmediate_operand" "register_operand")
     127                 :            : (define_subst_attr "round_prefix" "round" "vex" "evex")
     128                 :            : (define_subst_attr "round_mode512bit_condition" "round" "1" "(<MODE>mode == V16SFmode
     129                 :            :                                                               || <MODE>mode == V8DFmode
     130                 :            :                                                               || <MODE>mode == V8DImode
     131                 :            :                                                               || <MODE>mode == V16SImode)")
     132                 :            : (define_subst_attr "round_modev8sf_condition" "round" "1" "(<MODE>mode == V8SFmode)")
     133                 :            : (define_subst_attr "round_modev4sf_condition" "round" "1" "(<MODE>mode == V4SFmode)")
     134                 :            : (define_subst_attr "round_codefor" "round" "*" "")
     135                 :            : (define_subst_attr "round_opnum" "round" "5" "6")
     136                 :            : 
     137                 :            : (define_subst "round"
     138                 :            :   [(set (match_operand:SUBST_A 0)
     139                 :            :         (match_operand:SUBST_A 1))]
     140                 :       9618 :   "TARGET_AVX512F"
     141                 :         35 :   [(set (match_dup 0)
     142                 :        612 :         (unspec:SUBST_A [(match_dup 1)
     143                 :       1038 :           (match_operand:SI 2 "const_4_or_8_to_11_operand")]
     144                 :       2567 :           UNSPEC_EMBEDDED_ROUNDING))
     145                 :       2567 : ])
     146                 :        836 : 
     147                 :       1377 : (define_subst_attr "round_saeonly_name" "round_saeonly" "" "_round")
     148                 :       1179 : (define_subst_attr "round_saeonly_mask_operand2" "mask" "%r2" "%r4")
     149                 :        514 : (define_subst_attr "round_saeonly_mask_operand3" "mask" "%r3" "%r5")
     150                 :        241 : (define_subst_attr "round_saeonly_mask_operand4" "mask" "%r4" "%r6")
     151                 :        639 : (define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%r4" "%r5")
     152                 :        392 : (define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%r5" "%r7")
     153                 :        884 : (define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%r2")
     154                 :         26 : (define_subst_attr "round_saeonly_op3" "round_saeonly" "" "%r3")
     155                 :        884 : (define_subst_attr "round_saeonly_op4" "round_saeonly" "" "%r4")
     156                 :         26 : (define_subst_attr "round_saeonly_op5" "round_saeonly" "" "%r5")
     157                 :         26 : (define_subst_attr "round_saeonly_op6" "round_saeonly" "" "%r6")
     158                 :        283 : (define_subst_attr "round_saeonly_prefix" "round_saeonly" "vex" "evex")
     159                 :       1610 : (define_subst_attr "round_saeonly_mask_op2" "round_saeonly" "" "<round_saeonly_mask_operand2>")
     160                 :        232 : (define_subst_attr "round_saeonly_mask_op3" "round_saeonly" "" "<round_saeonly_mask_operand3>")
     161                 :        232 : (define_subst_attr "round_saeonly_mask_op4" "round_saeonly" "" "<round_saeonly_mask_operand4>")
     162                 :        463 : (define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "<round_saeonly_mask_scalar_merge_operand4>")
     163                 :        400 : (define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>")
     164                 :        400 : (define_subst_attr "round_saeonly_mask_arg3" "round_saeonly" "" ", operands[<mask_expand_op3>]")
     165                 :        400 : (define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v")
     166                 :        400 : (define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v")
     167                 :        400 : (define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "vector_operand" "register_operand")
     168                 :        400 : (define_subst_attr "round_saeonly_nimm_scalar_predicate" "round_saeonly" "nonimmediate_operand" "register_operand")
     169                 :            : (define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(<MODE>mode == V16SFmode
     170                 :         80 :                                                                               || <MODE>mode == V8DFmode
     171                 :         80 :                                                                               || <MODE>mode == V8DImode
     172                 :            :                                                                               || <MODE>mode == V16SImode)")
     173                 :         80 : (define_subst_attr "round_saeonly_modev8sf_condition" "round_saeonly" "1" "(<MODE>mode == V8SFmode)")
     174                 :            : 
     175                 :         40 : (define_subst "round_saeonly"
     176                 :         40 :   [(set (match_operand:SUBST_A 0)
     177                 :         77 :         (match_operand:SUBST_A 1))]
     178                 :       6476 :   "TARGET_AVX512F"
     179                 :         64 :   [(set (match_dup 0)
     180                 :            :         (unspec:SUBST_A [(match_dup 1)
     181                 :            :           (match_operand:SI 2 "const48_operand")]
     182                 :       1320 :           UNSPEC_EMBEDDED_ROUNDING))
     183                 :       1320 : ])
     184                 :        237 : 
     185                 :            : (define_subst "round_saeonly"
     186                 :        632 :   [(set (match_operand:CCFP 0)
     187                 :        632 :         (match_operand:CCFP 1))]
     188                 :            :   "TARGET_AVX512F"
     189                 :        632 :   [(set (match_dup 0)
     190                 :        632 :         (unspec:CCFP [(match_dup 1)
     191                 :        632 :           (match_operand:SI 2 "const48_operand")]
     192                 :        632 :           UNSPEC_EMBEDDED_ROUNDING))
     193                 :        632 : ])
     194                 :        632 : 
     195                 :        632 : (define_subst_attr "round_expand_name" "round_expand" "" "_round")
     196                 :        632 : (define_subst_attr "round_expand_nimm_predicate" "round_expand" "nonimmediate_operand" "register_operand")
     197                 :        632 : (define_subst_attr "round_expand_operand" "round_expand" "" ", operands[5]")
     198                 :            : 
     199                 :        632 : (define_subst "round_expand"
     200                 :        527 :  [(match_operand:SUBST_V 0)
     201                 :        105 :   (match_operand:SUBST_V 1)
     202                 :        527 :   (match_operand:SUBST_V 2)
     203                 :        632 :   (match_operand:SUBST_V 3)
     204                 :            :   (match_operand:SUBST_S 4)]
     205                 :        229 :   "TARGET_AVX512F"
     206                 :         53 :   [(match_dup 0)
     207                 :         53 :    (match_dup 1)
     208                 :        176 :    (match_dup 2)
     209                 :        176 :    (match_dup 3)
     210                 :        176 :    (match_dup 4)
     211                 :        176 :    (unspec [(match_operand:SI 5 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)])
     212                 :        176 : 
     213                 :            : (define_subst_attr "round_saeonly_expand_name" "round_saeonly_expand" "" "_round")
     214                 :         95 : (define_subst_attr "round_saeonly_expand_nimm_predicate" "round_saeonly_expand" "nonimmediate_operand" "register_operand")
     215                 :         95 : (define_subst_attr "round_saeonly_expand_operand6" "round_saeonly_expand" "" ", operands[6]")
     216                 :         95 : 
     217                 :            : (define_subst "round_saeonly_expand"
     218                 :            :  [(match_operand:SUBST_V 0)
     219                 :            :   (match_operand:SUBST_V 1)
     220                 :            :   (match_operand:SUBST_V 2)
     221                 :            :   (match_operand:SUBST_A 3)
     222                 :            :   (match_operand:SI 4)
     223                 :            :   (match_operand:SUBST_S 5)]
     224                 :            :   "TARGET_AVX512F"
     225                 :            :   [(match_dup 0)
     226                 :            :    (match_dup 1)
     227                 :            :    (match_dup 2)
     228                 :            :    (match_dup 3)
     229                 :            :    (match_dup 4)
     230                 :            :    (match_dup 5)
     231                 :            :    (unspec [(match_operand:SI 6 "const48_operand")] UNSPEC_EMBEDDED_ROUNDING)])
     232                 :            : 
     233                 :            : (define_subst_attr "mask_expand4_name" "mask_expand4" "" "_mask")
     234                 :            : (define_subst_attr "mask_expand4_args" "mask_expand4" "" ", operands[4], operands[5]")
     235                 :            : 
     236                 :            : (define_subst "mask_expand4"
     237                 :            :   [(match_operand:SUBST_V 0)
     238                 :            :    (match_operand:SUBST_V 1)
     239                 :            :    (match_operand:SUBST_V 2)
     240                 :            :    (match_operand:SI 3)]
     241                 :            :    "TARGET_AVX512VL"
     242                 :            :    [(match_dup 0)
     243                 :            :     (match_dup 1)
     244                 :            :     (match_dup 2)
     245                 :            :     (match_dup 3)
     246                 :            :     (match_operand:SUBST_V 4 "nonimm_or_0_operand")
     247                 :            :     (match_operand:<avx512fmaskmode> 5 "register_operand")])
     248                 :            : 
     249                 :            : (define_subst_attr "mask_scalar_name" "mask_scalar" "" "_mask")
     250                 :            : (define_subst_attr "mask_scalar_operand3" "mask_scalar" "" "%{%4%}%N3")
     251                 :            : (define_subst_attr "mask_scalar_operand4" "mask_scalar" "" "%{%5%}%N4")
     252                 :            : 
     253                 :            : (define_subst "mask_scalar"
     254                 :            :   [(set (match_operand:SUBST_V 0)
     255                 :            :         (vec_merge:SUBST_V
     256                 :            :           (match_operand:SUBST_V 1)
     257                 :            :           (match_operand:SUBST_V 2)
     258                 :            :           (const_int 1)))]
     259                 :        525 :   "TARGET_AVX512F"
     260                 :          8 :   [(set (match_dup 0)
     261                 :            :         (vec_merge:SUBST_V
     262                 :            :           (vec_merge:SUBST_V
     263                 :        532 :             (match_dup 1)
     264                 :        532 :             (match_operand:SUBST_V 3 "nonimm_or_0_operand" "0C")
     265                 :        370 :             (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
     266                 :            :           (match_dup 2)
     267                 :            :           (const_int 1)))])
     268                 :            : 
     269                 :            : (define_subst_attr "round_scalar_name" "round_scalar" "" "_round")
     270                 :            : (define_subst_attr "round_scalar_mask_operand3" "mask_scalar" "%R3" "%R5")
     271                 :            : (define_subst_attr "round_scalar_mask_op3" "round_scalar" "" "<round_scalar_mask_operand3>")
     272                 :            : (define_subst_attr "round_scalar_constraint" "round_scalar" "vm" "v")
     273                 :            : (define_subst_attr "round_scalar_prefix" "round_scalar" "vex" "evex")
     274                 :            : (define_subst_attr "round_scalar_nimm_predicate" "round_scalar" "nonimmediate_operand" "register_operand")
     275                 :            : 
     276                 :            : (define_subst "round_scalar"
     277                 :            :   [(set (match_operand:SUBST_V 0)
     278                 :            :         (vec_merge:SUBST_V
     279                 :            :           (match_operand:SUBST_V 1)
     280                 :            :           (match_operand:SUBST_V 2)
     281                 :            :           (const_int 1)))]
     282                 :        171 :   "TARGET_AVX512F"
     283                 :          0 :   [(set (match_dup 0)
     284                 :            :         (unspec:SUBST_V [
     285                 :            :              (vec_merge:SUBST_V
     286                 :        171 :                 (match_dup 1)
     287                 :        171 :                 (match_dup 2)
     288                 :            :                 (const_int 1))
     289                 :            :              (match_operand:SI 3 "const_4_or_8_to_11_operand")]
     290                 :            :                 UNSPEC_EMBEDDED_ROUNDING))])
     291                 :            : 
     292                 :            : (define_subst_attr "round_saeonly_scalar_name" "round_saeonly_scalar" "" "_round")
     293                 :            : (define_subst_attr "round_saeonly_scalar_mask_operand3" "mask_scalar" "%r3" "%r5")
     294                 :            : (define_subst_attr "round_saeonly_scalar_mask_operand4" "mask_scalar" "%r4" "%r6")
     295                 :            : (define_subst_attr "round_saeonly_scalar_mask_op3" "round_saeonly_scalar" "" "<round_saeonly_scalar_mask_operand3>")
     296                 :            : (define_subst_attr "round_saeonly_scalar_mask_op4" "round_saeonly_scalar" "" "<round_saeonly_scalar_mask_operand4>")
     297                 :            : (define_subst_attr "round_saeonly_scalar_constraint" "round_saeonly_scalar" "vm" "v")
     298                 :            : (define_subst_attr "round_saeonly_scalar_prefix" "round_saeonly_scalar" "vex" "evex")
     299                 :            : (define_subst_attr "round_saeonly_scalar_nimm_predicate" "round_saeonly_scalar" "nonimmediate_operand" "register_operand")
     300                 :            : 
     301                 :            : (define_subst "round_saeonly_scalar"
     302                 :            :   [(set (match_operand:SUBST_V 0)
     303                 :            :         (vec_merge:SUBST_V
     304                 :            :           (match_operand:SUBST_V 1)
     305                 :            :           (match_operand:SUBST_V 2)
     306                 :            :           (const_int 1)))]
     307                 :         83 :   "TARGET_AVX512F"
     308                 :         51 :   [(set (match_dup 0)
     309                 :            :         (unspec:SUBST_V [
     310                 :            :              (vec_merge:SUBST_V
     311                 :        275 :                 (match_dup 1)
     312                 :        275 :                 (match_dup 2)
     313                 :         99 :                 (const_int 1))
     314                 :            :              (match_operand:SI 3 "const48_operand")]
     315                 :            :                 UNSPEC_EMBEDDED_ROUNDING))])
     316                 :            : 
     317                 :            : (define_subst_attr "maskz_half_name" "maskz_half" "" "_maskz_1")
     318                 :            : (define_subst_attr "maskz_half_operand4" "maskz_half" "" "%{%5%}%N4")
     319                 :            : 
     320                 :            : (define_subst "maskz_half"
     321                 :            :   [(set (match_operand:SUBST_V 0)
     322                 :            :         (match_operand:SUBST_V 1))]
     323                 :            :   ""
     324                 :            :   [(set (match_dup 0)
     325                 :            :         (vec_merge:SUBST_V
     326                 :            :           (match_dup 1)
     327                 :            :           (match_operand:SUBST_V 2 "const0_operand" "C")
     328                 :            :           (match_operand:<avx512fmaskhalfmode> 3 "register_operand" "Yk")))])

Generated by: LCOV version 1.0

LCOV profile is generated on x86_64 machine using following configure options: configure --disable-bootstrap --enable-coverage=opt --enable-languages=c,c++,fortran,go,jit,lto --enable-host-shared. GCC test suite is run with the built compiler.